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    Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies
    52.
    发明授权
    Integrated assemblies having shield lines between digit lines, and methods of forming integrated assemblies 有权

    公开(公告)号：US11069687B2

    公开(公告)日：2021-07-20

    申请号：US16809924

    申请日：2020-03-05

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Srinivas Pulugurtha ,  Richard J. Hill ,  Yunfei Gao ,  Nicholas R. Tapias ,  Litao Yang ,  Haitao Liu

    IPC: H01L27/108

    Abstract: Some embodiments include an integrated assembly having digit lines which extend along a first direction, and which are spaced from one another by intervening regions. Each of the intervening regions has a first width along a cross-section. Pillars extend upwardly from the digit lines; and the pillars include transistor channel regions extending vertically between upper and lower source/drain regions. Storage elements are coupled with the upper source/drain regions. Wordlines extend along a second direction which crosses the first direction. The wordlines include gate regions adjacent the channel regions. Shield lines are within the intervening regions and extend along the first direction. The shield lines may be coupled with at least one reference voltage node. Some embodiments include methods of forming integrated assemblies.

    Memory arrays comprising memory cells
    53.
    发明授权
    Memory arrays comprising memory cells 有权

    公开(公告)号：US11043499B2

    公开(公告)日：2021-06-22

    申请号：US16192462

    申请日：2018-11-15

    Applicant: Micron Technology, inc.

    Inventor： Sanh D. Tang ,  Martin C. Roberts ,  Gurtej S. Sandhu

    IPC: H01L27/108 ,  H01L29/786

    Abstract: Some embodiments include a memory array having vertically-stacked memory cells. Each of the memory cells includes a transistor coupled with a charge-storage device, and each of the transistors has channel material with a bandgap greater than 2 electron-volts. Some embodiments include a memory array having digit lines extending along a vertical direction and wordlines extending along a horizontal direction. The memory array includes memory cells, with each of the memory cells being uniquely addressed by combination of one of the digit lines and one of the wordlines. Each of the memory cells includes a transistor which has GaP channel material. Each of the transistors has first and second source/drain regions spaced from one another by the GaP channel material. The first source/drain regions are coupled with the digit lines, and each of the memory cells includes a capacitor coupled with the second source/drain region of the associated transistor. Other embodiments are disclosed.

    Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related memory devices and electronic systems
    55.
    发明授权
    Methods of forming semiconductor devices using aspect ratio dependent etching effects, and related memory devices and electronic systems 有权

    公开(公告)号：US10991700B2

    公开(公告)日：2021-04-27

    申请号：US16793888

    申请日：2020-02-18

    Applicant: Micron Technology, Inc.

    Inventor： Song Guo ,  Sanh D. Tang ,  Vlad Temchenko ,  Shivani Srivastava

    IPC: H01L27/108 ,  H01L21/308 ,  G11C11/408

    Abstract: A method of forming a semiconductor device comprises forming a patterned masking material comprising parallel structures and parallel trenches extending at a first angle from about 30° to about 75° relative to a lateral direction. A mask is provided over the patterned masking material and comprises additional parallel structures and parallel apertures extending at a second, different angle from about 0° to about 90° relative to the lateral direction. The patterned masking material is further patterned using the mask to form a patterned masking structure comprising elongate structures separated by the parallel trenches and additional parallel trenches. Exposed portions of a hard mask material underlying the patterned masking structure are subjected to ARDE to form a patterned hard mask material. Exposed portions of a semiconductive material underlying the patterned hard mask material are removed to form semiconductive pillar structures. Semiconductor devices and electronic systems are also described.

    Memory arrays
    56.
    发明授权
    Memory arrays 有权

    公开(公告)号：US10950618B2

    公开(公告)日：2021-03-16

    申请号：US16204224

    申请日：2018-11-29

    Applicant: Micron Technology, Inc.

    Inventor： Sanh D. Tang ,  Richard J. Hill ,  Yi Fang Lee ,  Martin C. Roberts

    IPC: H01L27/11582 ,  H01L27/11585 ,  H01L27/11514 ,  G06F3/06

    Abstract: A memory array comprises vertically-alternating tiers of insulative material and memory cells. The memory cells individually comprise a transistor comprising first and second source/drain regions having a channel region there-between and a gate operatively proximate the channel region. The individual memory cells comprise a capacitor comprising first and second electrodes having a capacitor insulator there-between. The first electrode electrically couples to the first source/drain region. Wordline structures extend elevationally through the insulative material and the memory cells of the vertically-alternating tiers. Individual of the gates that are in different of the memory cell tiers directly electrically couple to individual of the wordline structures. Sense-lines electrically couple to multiple of the second source/drain regions of individual of the transistors. Other embodiments are disclosed.

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