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公开(公告)号：US20130300722A1
公开(公告)日：2013-11-14
申请号：US13981219
申请日：2012-01-23
IPC分类号： G09G3/36
CPC分类号： G09G3/3648 , G09G3/3611 , G09G3/3685 , G09G2310/0297
摘要： This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
摘要翻译： 该显示装置具有形成在液晶面板上的解复用器（501），该解复用器包括与视频信号线SL1〜SL3连接的三个时分驱动用开关元件SW1〜SW3。 这里，用于发送提供给耦合到视频信号线的开关元件的开关控制信号GS1至GS6的开关控制信号线的数量是时间分割数的两倍的开关控制信号线的数量和切换控制信号（例如GS1和 GS4）通过两个开关控制信号线分别发送，从而将作为负载耦合到开关控制信号线的开关元件的数量减半，导致控制信号的减少的波形舍入。
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公开(公告)号：US08223112B2
公开(公告)日：2012-07-17
申请号：US12734234
申请日：2008-08-18
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
摘要： At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3.
摘要翻译： 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止在单位电路中流过电流，并且还防止全通控制信号的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，使得第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。
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公开(公告)号：US20100309184A1
公开(公告)日：2010-12-09
申请号：US12734595
申请日：2008-08-20
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
摘要： A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
摘要翻译： 在至少一个实施例中，由多个n沟道晶体管构成的电路包括具有供给输入信号的漏极端子和提供输出信号的源极端子的晶体管（T1）; 以及具有提供控制信号的漏极端子和与晶体管（T1）的栅极端子连接的源极端子的晶体管（T2）。 晶体管（T2）的栅极端子连接到晶体管（T2）的源极端子。 通过该结构，可以提供（i）由具有相同导电类型并能够减小噪声影响的晶体管构成的半导体器件，以及（ii）包括半导体器件的显示器件。
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公开(公告)号：US20100259525A1
公开(公告)日：2010-10-14
申请号：US12734234
申请日：2008-08-18
CPC分类号： G11C19/28 , G09G3/20 , G09G3/3266 , G09G3/3275 , G09G3/3648 , G09G3/3674 , G09G3/3677 , G09G3/3685 , G09G3/3688 , G09G2300/0426 , G09G2310/0245 , G09G2310/0267 , G09G2310/0275 , G09G2310/0286 , G09G2310/0291
摘要： At least one embodiment of the present invention is directed to, even when external noise is applied to a shift register during all-on operation, preventing through-current from flowing in unit circuits and also to prevent increase in load on all-on control signal lines. When a high-level all-on control signal is provided to a unit circuit of a shift register, a transistor T3 is brought into off-state, so that a transistor T2 cannot output an on-voltage to a first output terminal. However, a transistor T24 is brought into on-state, so, that the first output terminal outputs an on-voltage to the exterior. On the other hand, a transistor T32 is brought into on-state, so that a second output terminal outputs an off-voltage to a unit circuit 11 in the next stage. At this time, the transistor T3 is kept in off-state, so that no through-current flows to the transistors T24 and T3. At least one embodiment of the present invention is suitable for driver circuits or suchlike of display devices and imaging devices.
摘要翻译： 本发明的至少一个实施例涉及即使当在全导通操作期间外部噪声被施加到移位寄存器时，也可以防止贯通电流在单元电路中流动，并且还防止全导通控制信号上的负载增加 线条。 当向移位寄存器的单元电路提供高电平全通控制信号时，晶体管T3进入截止状态，晶体管T2不能向第一输出端子输出导通电压。 然而，晶体管T24进入导通状态，因此，第一输出端子向外部输出导通电压。 另一方面，晶体管T32进入导通状态，使得第二输出端在下一级向单元电路11输出截止电压。 此时，晶体管T3保持截止状态，使得没有贯通电流流向晶体管T24和T3。 本发明的至少一个实施例适用于诸如显示装置和成像装置的驱动电路等。
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公开(公告)号：US08675811B2
公开(公告)日：2014-03-18
申请号：US12734595
申请日：2008-08-20
IPC分类号： G11C19/00
CPC分类号： G09G3/3677 , G09G2300/0408 , G09G2300/0426 , G09G2310/0289 , G11C19/28 , H01L27/124 , H03K17/161 , H03K17/162 , H03K17/687
摘要： A circuit which is constituted by a plurality of n-channel transistors includes, in at least one embodiment, a transistor (T1) which has a drain terminal to which an input signal is supplied and a source terminal from which a output signal is supplied; and a transistor (T2) which has a drain terminal to which a control signal is supplied and a source terminal connected to a gate terminal of the transistor (T1). A gate terminal of the transistor (T2) is connected to the source terminal of the transistor (T2). With the arrangement, it is possible to provide (i) a semiconductor device which is constituted by transistors having an identical conductivity type and which is capable of reducing an influence of noise, and (ii) a display device including the semiconductor device.
摘要翻译： 在至少一个实施例中，由多个n沟道晶体管构成的电路包括具有供给输入信号的漏极端子和提供输出信号的源极端子的晶体管（T1）; 以及具有提供控制信号的漏极端子和与晶体管（T1）的栅极端子连接的源极端子的晶体管（T2）。 晶体管（T2）的栅极端子连接到晶体管（T2）的源极端子。 通过该结构，可以提供（i）由具有相同导电类型并能够减小噪声影响的晶体管构成的半导体器件，以及（ii）包括半导体器件的显示器件。
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公开(公告)号：US08269713B2
公开(公告)日：2012-09-18
申请号：US12733117
申请日：2008-05-15
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US20100141641A1
公开(公告)日：2010-06-10
申请号：US12733117
申请日：2008-05-15
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US08493312B2
公开(公告)日：2013-07-23
申请号：US13571608
申请日：2012-08-10
IPC分类号： G09G3/36
CPC分类号： G11C19/184 , G09G3/3677 , G09G3/3688 , G09G2310/0286 , G09G2330/021
摘要： In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.
摘要翻译： 在本发明的一个实施例中，移位寄存器的单元电路包括配置有晶体管T1，晶体管T2和电容器的晶体管T3，晶体管T4和复位信号产生电路的自举电路。 通过使用两相时钟信号并且其高电平周期彼此不重叠，复位信号产生电路产生在正常状态下处于高电平的复位信号，并且当输入信号变为低电平时变为低电平 进入高层。 在复位信号为高电平的期间，晶体管T3，T4进行节点的放电，输出信号的下拉。 因此，可以获得省电移位寄存器，其将正常状态下的输出信号固定在低电平，而不允许通流通过。
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公开(公告)号：US20120249499A1
公开(公告)日：2012-10-04
申请号：US13513017
申请日：2010-10-07
IPC分类号： G06F3/038
CPC分类号： G09G3/006 , G09G3/3611 , G09G3/3688 , G09G2310/0297 , G09G2330/12
摘要： A one-input and three-output demultiplexer that includes sampling switches for sampling a video signal is provided at one end side of source bus lines, and a one-input and three-output demultiplexer that includes test switches provided corresponding to sampling switches and that uses a test video signal as an input signal is provided at the other end side of the source bus lines. When an any control signal out of three control signals for controlling states of a sampling switch and a test switch is defined as a target control signal, a source bus line connected to the sampling switch which is set to an on state by the target control signal and a source bus line connected to the test switch which is set to an on state by the target control signal are different.
摘要翻译： 在源总线的一端提供包括用于采样视频信号的采样开关的单输入和三输出解复用器，以及包括与采样开关相对应的测试开关的单输入和三输出解复用器，并且 使用测试视频信号作为输入信号设置在源总线的另一端。 当将用于控制采样开关和测试开关的状态的三个控制信号中的任何控制信号定义为目标控制信号时，连接到通过目标控制信号被设置为导通状态的采样开关的源极总线 并且连接到由目标控制信号设置为接通状态的测试开关的源极总线不同。
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公开(公告)号：US20100244946A1
公开(公告)日：2010-09-30
申请号：US12734044
申请日：2008-08-26
IPC分类号： H01L25/00
CPC分类号： G09G3/3677 , G09G3/3655 , G09G2310/0286 , G09G2310/0289 , G09G2310/0291 , G11C19/184 , G11C19/28 , H03K17/063 , H03K17/165 , H03K17/693
摘要： A circuit is constituted by a plurality of n-channel-type transistors, the circuit including: among the plurality of transistors, a transistor including a drain terminal for receiving a voltage of VDD, a source terminal, and a gate terminal for receiving an input signal; among the plurality of transistors, a transistor including a drain terminal for receiving the voltage of VDD, a source terminal connected to an output terminal, and a gate terminal connected to the source terminal of the transistor; and a capacitor provided between a node and a clock terminal for receiving a clock signal. In at least one embodiment, the clock signal inputted into the clock terminal has a frequency higher than that of an output signal outputted from the output terminal. Therefore, it is possible to provide: a semiconductor device constituted by transistors of the same conductivity type, which semiconductor device can output a stable signal by preventing a reduction in electric potential level; and a display device including the semiconductor device.
摘要翻译： 电路由多个n沟道型晶体管构成，所述电路包括：在所述多个晶体管中，包括用于接收VDD电压的漏极端子的晶体管，源极端子和用于接收输入的栅极端子 信号; 在多个晶体管中，包括用于接收VDD的电压的漏极端子，连接到输出端子的源极端子和连接到晶体管的源极端子的栅极端子的晶体管; 以及设置在节点和时钟端子之间用于接收时钟信号的电容器。 在至少一个实施例中，输入到时钟端的时钟信号的频率高于从输出端输出的输出信号的频率。 因此，可以提供：由相同导电类型的晶体管构成的半导体器件，该半导体器件可以通过防止电位电平的降低而输出稳定的信号; 以及包括半导体器件的显示装置。
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