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公开(公告)号：US20080178183A1
公开(公告)日：2008-07-24
申请号：US12055179
申请日：2008-03-25
IPC分类号： G06F9/46
CPC分类号： G06F9/4812
摘要： Scheduling threads in a multi-processor computer system including establishing an interrupt threshold for a thread, where the interrupt threshold represents a maximum permissible number of interrupts during thread execution on a processor; executing the thread on a current processor, where the thread has thread affinity for one or more processors including the current processor; counting a number of interrupts during execution of the thread on the current processor; and removing thread affinity for the current processor in dependence upon the counted number of interrupts and the interrupt threshold.
摘要翻译： 在多处理器计算机系统中调度线程，包括建立线程的中断阈值，其中中断阈值表示在处理器上的线程执行期间的最大允许中断次数; 在当前处理器上执行线程，其中线程对于包括当前处理器的一个或多个处理器具有线程亲和性; 在当前处理器上的线程执行期间对多个中断进行计数; 并根据计数的中断次数和中断阈值去除当前处理器的线程亲和度。
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公开(公告)号：US20080098397A1
公开(公告)日：2008-04-24
申请号：US11955503
申请日：2007-12-13
申请人： Jos Accapadi , Andrew Dunshea , Dirk Michel , Mysore Srinivas
发明人： Jos Accapadi , Andrew Dunshea , Dirk Michel , Mysore Srinivas
IPC分类号： G06F9/46
CPC分类号： G06F9/5083
摘要： A system and method for scheduling threads in a Simultaneous Multithreading (SMT) processor environment utilizing multiple SMT processors is provided. Poor performing threads that are being run on each of the SMT processors are identified. After being identified, the poor performing threads are moved to a different SMT processor. Data is captured regarding the performance of threads. In one embodiment, this data includes each threads' CPI value. When a thread is moved, data regarding the thread and its performance at the time it was moved is recorded along with a timestamp. The data regarding previous moves is used to determine whether a thread's performance is improved following the move.
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53.发明授权System and method for scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval 有权用于在同步多线程处理器中调度兼容线程的系统和方法，使用在指定时间间隔期间的每个指令值周期公开(公告)号：US07360218B2
公开(公告)日：2008-04-15
申请号：US10671132
申请日：2003-09-25
CPC分类号： G06F9/4881 , G06F2209/483
摘要： A system and method for identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.
摘要翻译： 通过计算在SMT处理器上运行两个线程时发生的性能指标（例如每个指令周期（CPI）），可以提供用于在同时多线程（SMT）处理器环境中识别兼容线程的系统和方法。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值，则记录指示兼容性的信息。 当线程即将完成时，调度程序将查看完成线程所属的运行队列，以调度另一个线程。 调度程序标识（1）与SMT处理器上仍然运行的线程（即，即将完成的线程）兼容的线程，以及（2）准备执行。 持续更新CPI数据，以便不断地识别彼此兼容的线程。
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54.发明申请Method to improve system DMA mapping while substantially reducing memory fragmentation 失效改进系统DMA映射同时显着减少内存碎片的方法公开(公告)号：US20070245041A1
公开(公告)日：2007-10-18
申请号：US11385926
申请日：2006-03-21
申请人： Binh Hua , Hong Hua , Dirk Michel , Wen Xiong
发明人： Binh Hua , Hong Hua , Dirk Michel , Wen Xiong
IPC分类号： G06F13/28
CPC分类号： G06F13/28
摘要： A method, system and computer program product for eliminating the latency in searching for contiguous memory space by an IO DMA request of a device driver. Three new application programming interfaces (APIs) are provided within the operating system (OS) code that allows the device driver(s) to (1) pre-request and pre-allocate the IO DMA address range from the OS during the IPL and maintain control of the address, (2) map a system (virtual/physical) address range to a specific pre-allocated IO DMA address range, and (3) free the pre-allocated IO DMA address space back to the kernel when the space is no longer required. Utilizing these APIs enables advanced IO DMA address mapping techniques maintained by the device drivers, and the assigned/allocated IO DMA address space is no longer fragmented, and the latency of completing the IO DMA mapping is substantially reduced/eliminated.
摘要翻译： 一种方法，系统和计算机程序产品，用于消除通过设备驱动程序的IO DMA请求搜索连续存储器空间的延迟。 在操作系统（OS）代码中提供了三个新的应用编程接口（API），允许设备驱动程序（1）在IPL期间从OS预先请求并预分配IO DMA地址范围并维护 控制地址，（2）将系统（虚拟/物理）地址范围映射到特定的预先分配的IO DMA地址范围，以及（3）当空间为空时将预分配的IO DMA地址空间释放回内核 不再需要。 利用这些API可以实现由设备驱动程序维护的高级IO DMA地址映射技术，并且分配/分配的IO DMA地址空间不再分段，并且完全减少/消除了完成IO DMA映射的延迟。
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公开(公告)号：US20050278488A1
公开(公告)日：2005-12-15
申请号：US10865702
申请日：2004-06-10
申请人： Diane Flemming , Octavian Herescu , Agustin Mena , Dirk Michel
发明人： Diane Flemming , Octavian Herescu , Agustin Mena , Dirk Michel
IPC分类号： G06F12/02 , G06F9/46 , G06F9/50 , G06F12/00 , G06F15/163
CPC分类号： G06F9/5077
摘要： A method, apparatus, and computer instructions for transferring data. The data in a first partition is received within a memory region assigned to the first partition in the logical partitioned data processing system to form received data. The memory region is assigned to a second partition, in response to a determination that the received data is for the second partition. The second partition may then access the data in the memory region.
摘要翻译： 一种用于传输数据的方法，装置和计算机指令。 在分配给逻辑分区数据处理系统中的第一分区的存储器区域内接收第一分区中的数据，以形成接收的数据。 响应于确定所接收的数据是用于第二分区，将存储器区域分配给第二分区。 然后，第二分区可以访问存储器区域中的数据。
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公开(公告)号：US09354934B2
公开(公告)日：2016-05-31
申请号：US13343920
申请日：2012-01-05
CPC分类号： G06F9/5033 , G06F9/4812 , G06F9/5061 , G06F9/5077 , G06F11/2092 , G06F2212/152
摘要： Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.
摘要翻译： 在多个虚拟处理器之间管理中断密集型和中断驱动的过程，其中每个虚拟处理器与物理处理器相关联，其中每个物理处理器可以与多个虚拟处理器相关联，并且其中每个虚拟处理器的任务是 执行一个或多个处理，通过确定在多个虚拟处理器中执行的多个处理中的哪一个正在或已经被操作时间中的至少最小中断计数驱动; 选择所述多个虚拟处理器的子集以形成隔离池; 将中断密集型进程迁移到虚拟处理器的隔离池; 并由计算机命令将中断的传送或路由偏移到虚拟处理器的隔离池。
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57.发明授权Optimizing power management in multicore virtual machine platforms by dynamically variable delay before switching processor cores into a low power state 失效在将处理器内核切换到低功耗状态之前，通过动态可变延迟优化多核虚拟机平台中的电源管理公开(公告)号：US08327176B2
公开(公告)日：2012-12-04
申请号：US12751227
申请日：2010-03-31
IPC分类号： G06F1/32
CPC分类号： G06F1/3228 , G06F1/3287 , G06F1/329 , G06F9/5094 , Y02D10/171 , Y02D10/22 , Y02D10/24
摘要： Distributing a thread for running on a physical processor and enabling the physical processor to be switched into a low power snooze state when said running thread is IDLE. However, this switching into said low power state is enabled to be delayed by a delay time from an IDLE dispatch from said running thread; such delay is determined by tracking the rate of the number of said IDLE dispatches per processor clock interval and dynamically varying said delay time wherein the delay time is decreased when said rate of IDLE dispatches increases and the delay time is increased when said rate of IDLE dispatches decreases.
摘要翻译： 分配线程以在物理处理器上运行，并使物理处理器在所述运行的线程为空闲时切换到低功耗打盹状态。 然而，切换到所述低功率状态的能力可以延迟来自所述运行线程的IDLE分派的延迟时间; 这样的延迟通过跟踪每个处理器时钟间隔的所述IDLE调度的数量的速率来确定，并且动态地改变所述延迟时间，其中当所述IDLE调度的速率增加时延迟时间减小并且当所述IDLE调度速率增加时延迟时间增加 减少
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58.发明申请公开(公告)号：US20120204186A1
公开(公告)日：2012-08-09
申请号：US13023550
申请日：2011-02-09
IPC分类号： G06F9/50
CPC分类号： G06F9/5077 , G06F9/4881
摘要： An operating system or virtual machine of an information handling system (IHS) initializes a resource manager to provide processor resource utilization management during workload or application execution. The resource manager captures short term interval (STI) and long term interval (LTI) processor resource utilization data and stores that utilization data within an information store of the virtual machine. If a capacity on demand mechanism is enabled, the resource manager modifies a reserved capacity value. The resource manager selects previous STI and LTI values for comparison with current resource utilization and may apply a safety margin to generate a reserved capacity or target resource utilization value for the next short term interval (STI). The hypervisor may modify existing virtual processor allocation to match the target resource utilization.
摘要翻译： 信息处理系统（IHS）的操作系统或虚拟机初始化资源管理器，以在工作负载或应用程序执行期间提供处理器资源利用管理。 资源管理器捕获短期间隔（STI）和长期间隔（LTI）处理器资源利用率数据，并将该利用率数据存储在虚拟机的信息存储区内。 如果启用了按需容量机制，则资源管理器将修改保留的容量值。 资源管理器选择先前的STI和LTI值以与当前资源利用率进行比较，并且可以应用安全余量来生成下一个短期间隔（STI）的预留容量或目标资源利用率值。 管理程序可以修改现有的虚拟处理器分配以匹配目标资源利用率。
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公开(公告)号：US08132178B2
公开(公告)日：2012-03-06
申请号：US11943649
申请日：2007-11-21
IPC分类号： G06F9/46
CPC分类号： G06F9/52 , G06F9/4818
摘要： A system and method is provided for delaying a priority boost of an execution thread. When a thread prepares to enter a critical section of code, such as when the thread utilizes a shared system resource, a user mode accessible data area is updated indicating that the thread is in a critical section and, if the kernel receives a preemption event, the priority boost that the thread should receive. If the kernel receives a preemption event before the thread finishes the critical section, the kernel applies the priority boost on behalf of the thread. Often, the thread will finish the critical section without having to have its priority actually boosted. If the thread does receive an actual priority boost then, after the critical section is finished, the kernel resets the thread's priority to a normal level.
摘要翻译： 提供了一种用于延迟执行线程的优先级提升的系统和方法。 当线程准备进入代码的关键部分时，例如当线程利用共享系统资源时，更新用户模式可访问数据区域，指示线程处于关键部分，并且如果内核接收到抢占事件， 线程应该接收的优先级提升。 如果内核在线程完成关键部分之前收到抢占事件，则内核将代表线程应用优先级提升。 通常，线程将完成关键部分，而无需实际提升优先级。 如果线程确实接收到实际的优先级提升，那么在关键部分完成之后，内核会将线程的优先级重置为正常级别。
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60.发明授权Scheduling compatible threads in a simultaneous multi-threading processor using cycle per instruction value occurred during identified time interval 有权在指定的时间间隔内，使用每个指令周期的周期调度同时多线程处理器中的兼容线程公开(公告)号：US07698707B2
公开(公告)日：2010-04-13
申请号：US12036804
申请日：2008-02-25
CPC分类号： G06F9/4881 , G06F2209/483
摘要： Identifying compatible threads in a Simultaneous Multithreading (SMT) processor environment is provided by calculating a performance metric, such as cycles per instruction (CPI), that occurs when two threads are running on the SMT processor. The CPI that is achieved when both threads were executing on the SMT processor is determined. If the CPI that was achieved is better than the compatibility threshold, then information indicating the compatibility is recorded. When a thread is about to complete, the scheduler looks at the run queue from which the completing thread belongs to dispatch another thread. The scheduler identifies a thread that is (1) compatible with the thread that is still running on the SMT processor (i.e., the thread that is not about to complete), and (2) ready to execute. The CPI data is continually updated so that threads that are compatible with one another are continually identified.
摘要翻译： 通过计算在SMT处理器上运行两个线程时发生的性能指标（例如每个指令周期（CPI））来提供在同时多线程（SMT）处理器环境中识别兼容线程。 确定在两个线程在SMT处理器上执行时实现的CPI。 如果实现的CPI优于兼容性阈值，则记录指示兼容性的信息。 当线程即将完成时，调度程序将查看完成线程所属的运行队列，以调度另一个线程。 调度程序标识（1）与SMT处理器上仍然运行的线程（即，即将完成的线程）兼容的线程，以及（2）准备执行。 持续更新CPI数据，以便不断地识别彼此兼容的线程。
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