公开(公告)号：US06538584B2

公开(公告)日：2003-03-25

申请号：US09752883

申请日：2000-12-28

申请人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

发明人： Shekhar Y. Borkar ,  Matthew B. Haycock ,  Stephen R. Mooney ,  Aaron K. Martin ,  Joseph T. Kennedy

IPC分类号： H03M700

CPC分类号： G11C7/10

摘要： In some embodiments, the invention involves a circuit including a first set of conductors to carry a current bit set and last bit set circuitry to hold and provide a last bit set. The circuit also includes drivers coupled to interconnect conductors to provide signals from the drivers to the interconnect conductors and an encoder to receive the last bit set and the current bit set and determine whether to provide the current bit set or an encoded version of the current bit set to the drivers.

摘要翻译： 在一些实施例中，本发明涉及包括第一组导体的电路，以承载当前位组和最后位组电路以保持并提供最后位组。 电路还包括耦合到互连导体的驱动器以提供从驱动器到互连导体的信号，以及用于接收最后位组和当前位组的编码器，并确定是提供当前位组还是当前位的编码版本 设置为司机。

公开(公告)号：US06441649B1

公开(公告)日：2002-08-27

申请号：US09752647

申请日：2000-12-29

申请人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

发明人： Aaron K. Martin ,  Stephen R. Mooney ,  Joseph T. Kennedy ,  Matthew B. Haycock ,  Shekhar Y. Borkar

IPC分类号： G01R1900

CPC分类号： H03K3/356191 ,  H03K3/35613

摘要： The invention provides an apparatus, method and means for capturing data. In an aspect, a differential and complementary input folded-cascode clocked amplifier is provided. In an aspect, the invention provides rail-to-rail input common-mode voltage range. In an aspect, the invention provides a setup/hold time window that is smaller than the setup/hold time window of a conventional clocked amplifier and a conventional input amplifier with a separate amplifier and latch. In an aspect, the invention provides high common-mode rejection as compared with conventional clocked sense amplifiers.

摘要翻译： 本发明提供了一种用于捕获数据的装置，方法和装置。 在一方面，提供差分和互补输入折叠共源共栅时钟放大器。 在一方面，本发明提供轨至轨输入共模电压范围。 在一方面，本发明提供了一种建立/保持时间窗口，其小于常规时钟放大器和具有单独放大器和锁存器的常规输入放大器的建立/保持时间窗口。 在一方面，与传统的时钟感测放大器相比，本发明提供了高共模抑制。

公开(公告)号：US06366156B1

公开(公告)日：2002-04-02

申请号：US09451661

申请日：1999-11-30

申请人： Siva G. Narendra ,  Vivek K. De ,  Shekhar Y. Borkar

发明人： Siva G. Narendra ,  Vivek K. De ,  Shekhar Y. Borkar

IPC分类号： G05F110

CPC分类号： G05F3/205

摘要： In some embodiments, In some embodiments, the invention includes an electrical system having a functional unit block (FUB) including field effect transistors (FETs). A distributed forward body bias (FBB) voltage generation system provides at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant FBB. In some embodiments, the system includes a constant differential voltage generator and a distributed body bias generator to receive a set of differential signals from the constant differential voltage generator and provide at least one body bias signal to at least some of the FETs of the FUB such that the at least some of the FETs have a constant forward body bias. In some embodiments, the system includes multiple body bias generators coupled to corresponding FUBs receive a set of differential signals from a single constant differential voltage generator. In other embodiments, multiple constant differential voltage generators provide multiple sets of differential signals to multiple body bias generators coupled to corresponding FUBs. Without the invention, significant changes in the FBB of FETs in different FUBs can induce a new source of variation which can nullify the advantages of FBB and actually increase parameter variations between FETs of different FUBs.

摘要翻译： 在一些实施例中，在一些实施例中，本发明包括具有包括场效应晶体管（FET）的功能单元块（FUB）的电气系统。 分布式正向偏置（FBB）电压产生系统向FUB的至少一些FET提供至少一个体偏置信号，使得至少一些FET具有恒定的FBB。 在一些实施例中，该系统包括恒定差分电压发生器和分布式主体偏置发生器，以从该恒定差分电压发生器接收一组差分信号，并且向FUB的至少一些FET提供至少一个体偏置信号， 所述至少一些所述FET具有恒定的前向体偏置。 在一些实施例中，系统包括耦合到对应的FUB的多个体偏置发生器，其从单个恒定差分电压发生器接收一组差分信号。 在其他实施例中，多个恒定差分电压发生器向耦合到对应的FUB的多个体偏置发生器提供多组差分信号。 没有本发明，不同FUB中的FET的FBB的显着变化可以引起新的变化源，这可以消除FBB的优点，并且实际上增加了不同FUB的FET之间的参数变化。

公开(公告)号：US5634043A

公开(公告)日：1997-05-27

申请号：US295556

申请日：1994-08-25

申请人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

发明人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

IPC分类号： G06F15/173 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F15/17381

摘要： A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into "clusters" wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.

摘要翻译： 一种具有用于处理信息的至少第一微处理器和经由第一点对点接口耦合到第一微处理器的第一存储器的计算机系统。 第一点对点接口提供第一微处理器和第一存储器之间的信号通信，而与第一微处理器或第一存储器接收的信号的相位无关。 第一点对点接口包括用于接收来自第一存储器的信号的微处理器中的第一点对点电路。 第一点对点电路和微处理器在一些实现的实施例中包括单个集成电路，提供具有各种拓扑的系统的构造和设计的容易性。 第二微处理器还可以经由第二点对点接口耦合到第一存储器，第一微处理器和第二微处理器共享第一存储器以存储由第一微处理器和第二微处理器使用的信息。 在该配置中，第一存储器可以包括用于第一微处理器和第二微处理器的重复高速缓存存储器，以便为两个处理器提供高速缓存一致性。 该系统还可以包括经由第二点对点接口耦合到第一存储器的第一输入 - 输出设备。 处理器，存储器和输入/输出设备的各种拓扑可以被设计成“群集”，其中每个群集彼此通信用于访问远程和本地，用于访问输入/输出设备，以及用于维持高速缓存的一致性。

公开(公告)号：US5623644A

公开(公告)日：1997-04-22

申请号：US296019

申请日：1994-08-25

申请人： Keith-Michael W. Self ,  Shekhar Y. Borkar ,  Jerry G. Jex ,  Edward A. Burton ,  Stephen R. Mooney ,  Prantik K. Nag

发明人： Keith-Michael W. Self ,  Shekhar Y. Borkar ,  Jerry G. Jex ,  Edward A. Burton ,  Stephen R. Mooney ,  Prantik K. Nag

IPC分类号： G06F15/173 ,  G06F13/00 ,  G06F15/16

CPC分类号： G06F15/17381

摘要： A unidirectional point-to-point communication apparatus for communicating messages between two computing resources irrespective of the phase of the messages, length of a communication path between the two computing resources and internal speed of the two computing resources. The communication apparatus has a high speed communication bus coupling a transmitter and a receiver for transmitting the messages from the transmitter to the receiver. A high speed communication clock is coupled to the bus and the receiver for timing the messages transmitted on the high speed communication bus between transmitter and the receiver. A large data buffer is coupled to the high speed communication bus after the receiver for storing messages transmitted between the transmitter and the receiver. A buffer accessing circuit is coupled to the buffer for referencing write locations to store the messages received from the transmitter over the communication bus, and for referencing read locations for reading the messages out of the buffer by the receiver. Finally, a delay locked loop circuit is coupled to the communication bus, the buffer accessing circuit and the buffer for providing the proper set-up and hold time requirements for the messages transmitted on the communication bus from the transmitter and storing the messages in the buffer.

摘要翻译： 一种单向点对点通信装置，用于在两个计算资源之间传送消息，而不管消息的相位，两个计算资源之间的通信路径的长度以及两个计算资源的内部速度。 通信装置具有耦合发射机和接收机的高速通信总线，用于将消息从发射机发射到接收机。 高速通信时钟耦合到总线和接收器，用于定时在发射机和接收机之间的高速通信总线上发送的消息。 在用于存储在发射机和接收机之间传输的消息的接收机之后，大数据缓冲器耦合到高速通信总线。 缓冲器访问电路耦合到缓冲器，用于参考写入位置以存储通过通信总线从发送器接收的消息，并且用于参考由接收器读出缓冲器中的消息的读取位置。 最后，延迟锁定环路电路耦合到通信总线，缓冲器访问电路和缓冲器，用于为在通信总线上从发送器发送的消息提供适当的建立和保持时间要求，并将消息存储在缓冲器中 。

公开(公告)号：US4809167A

公开(公告)日：1989-02-28

申请号：US157104

申请日：1988-02-10

申请人： Martin B. Pawloski ,  Shekhar Y. Borkar

发明人： Martin B. Pawloski ,  Shekhar Y. Borkar

IPC分类号： G06F11/26 ,  G06F11/36 ,  G06F9/44

CPC分类号： G06F11/3652 ,  G06F11/261

摘要： An emulator circuit utilizes an Intel 8031 microprocessor with external address and data buses to emulate an Intel 8051 single chip microcomputer with no external buses by providing external registers into which the contents of the internal 8031 "Port 0" and "Port 2" registers are output and functionally "recreated". The external access (EA) lead is toggled to make the 8031 function as an 8051 during the states in which the 8051 samples its logic levels and destroys port 0 latches if configured as an 8031. Toggling the EA lead to a high level causes outputting the contents of the Port 0 and Port 2 latches to their respective leads. The emulator circuit generates a "Force Ports" pulse that causes the "recreated" port registers or the external circuitry to "force" external logic levels onto the 8031 Port 0 and Port 2 leads. The address latch enable (ALE) signal is delayed until after the Force Ports signal lapses to allow the internal Port 0 logic to generate address outputs on its leads as part of the external address bus.

摘要翻译： 仿真器电路采用具有外部地址和数据总线的Intel 8031微处理器，通过提供内部8031“端口0”和“端口2”寄存器的内容输出到其中的外部寄存器来模拟不带外部总线的Intel 8051单片机 并在功能上“重新创建”。 在8051采样其逻辑电平并且销毁端口0锁存器（如果配置为8031）的状态下，外部访问（EA）引脚被切换以使8031用作8051。将EA引线切换到高电平将导致输出 端口0和端口2的内容锁定到它们各自的引线。 仿真器电路产生“强制端口”脉冲，导致“重新创建”端口寄存器或外部电路将外部逻辑电平“强制”到8031端口0和端口2引线上。 地址锁存使能（ALE）信号被延迟，直到强制端口信号中断，允许内部端口0逻辑在其引线上产生地址输出作为外部地址总线的一部分。