公开(公告)号：US4503535A

公开(公告)日：1985-03-05

申请号：US393906

申请日：1982-06-30

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/00 ,  G06F11/07

CPC分类号： G06F11/2002 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0781 ,  G06F11/0784 ,  G06F11/1008 ,  G06F11/1076 ,  G06F11/1637 ,  G06F11/1658 ,  G06F11/1666 ,  G06F11/2028

摘要： A number of intelligent nodes (bus interface units-BIUs and memory control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Error-detection mechanisms deal with information flow occuring across area boundaries. Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error report lines (106, 108). If an error recurs the node at which the error exists initiates an error message which is received and repropagated on the error report lines by all nodes. The error message identifies the type of error and the node ID at which the error was detected. Confinement area isolation logic in a node isolates a faulty confinement area of which the node is a part, upon the condition that the node ID in an error report message identifies the node as a node which is a part of a faulty confinement area. Logic in the node reconfigures at least part of the system upon the condition that the node ID in the error report message identifies the node as a node which is part of a confinement area which should be recofigured to recover from the error reported in the error report message.

摘要翻译： 在由具有相应的错误报告和控制线（106）的处理器总线（105）组成的矩阵中提供了许多智能节点（总线接口单元-IBU和存储器控制单元-MCU）。 和具有对应的错误报告和控制线（108）的存储器总线（107）。 错误检测机制处理跨越区域边界的信息流。 每个节点（100,101,102,103）具有用于在错误报告行（106,108）上记录错误和报告错误的装置。 如果存在错误的节点发生错误，则会发出在所有节点的错误报告行上接收和重新传播的错误消息。 错误消息标识错误的类型和检测到错误的节点ID。 一个节点中的限制区域隔离逻辑将错误报告消息中的节点ID标识为作为故障限制区域的一部分的节点，从而隔离节点是其中一部分的故障限制区域。 节点中的逻辑重新配置系统的至少一部分，条件是错误报告消息中的节点ID将节点标识为节点，该节点是应重新配置的节点，以从错误报告中报告的错误中恢复 信息。

公开(公告)号：US4407016A

公开(公告)日：1983-09-27

申请号：US235470

申请日：1981-02-18

申请人： John A. Bayliss ,  Craig B. Peterson ,  Doran K. Wilde

发明人： John A. Bayliss ,  Craig B. Peterson ,  Doran K. Wilde

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F13/28 ,  G06F9/20

CPC分类号： G06F13/28 ,  G06F12/1036 ,  G06F12/1441 ,  G06F12/1081

摘要： A microprocessor receives addresses and data from a peripheral subsystem for use in subsequently accessing portions of the main memory of a data processing system in a controlled and protected manner. Each of the addresses is used to interrogate an associative memory to determine if the address falls within one of the subranges for a "window" on the main memory address space. If the address matches, then it is used to develop a corresponding address on the main memory address space. The data associated with the peripheral subsystem address is then passed through the interface and into the main memory at the translated memory address. Data transfer is improved by buffering blocks of data on the microprocessor. Data bytes are written into the buffer at a slower rate than data blocks are read out of the buffer and into main memory. A buffer bypass register allows single bytes of data to be transferred to a single address by bypassing the buffer. Address development and memory response signals are generated by the microprocessor rather than the peripheral subsystem processor for block transfers.

摘要翻译： 微处理器从外围子系统接收地址和数据，用于随后以受控和受保护的方式访问数据处理系统的主存储器的部分。 每个地址用于询问关联存储器以确定地址是否落在主存储器地址空间上的“窗口”的子范围内。 如果地址匹配，则用于在主存储器地址空间上开发相应的地址。 然后，与外围子系统地址相关联的数据通过接口传递到转换的存储器地址的主存储器中。 通过缓冲微处理器上的数据块来改善数据传输。 数据字节以比数据块从缓冲器读出并进入主存储器的速率慢的速率写入缓冲器。 缓冲旁路寄存器允许通过绕过缓冲区将单个字节的数据传输到单个地址。 地址开发和存储器响应信号由微处理器产生，而不是用于块传输的外围子系统处理器。

公开(公告)号：US5634043A

公开(公告)日：1997-05-27

申请号：US295556

申请日：1994-08-25

申请人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

发明人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

IPC分类号： G06F15/173 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F15/17381

摘要： A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into "clusters" wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.

摘要翻译： 一种具有用于处理信息的至少第一微处理器和经由第一点对点接口耦合到第一微处理器的第一存储器的计算机系统。 第一点对点接口提供第一微处理器和第一存储器之间的信号通信，而与第一微处理器或第一存储器接收的信号的相位无关。 第一点对点接口包括用于接收来自第一存储器的信号的微处理器中的第一点对点电路。 第一点对点电路和微处理器在一些实现的实施例中包括单个集成电路，提供具有各种拓扑的系统的构造和设计的容易性。 第二微处理器还可以经由第二点对点接口耦合到第一存储器，第一微处理器和第二微处理器共享第一存储器以存储由第一微处理器和第二微处理器使用的信息。 在该配置中，第一存储器可以包括用于第一微处理器和第二微处理器的重复高速缓存存储器，以便为两个处理器提供高速缓存一致性。 该系统还可以包括经由第二点对点接口耦合到第一存储器的第一输入 - 输出设备。 处理器，存储器和输入/输出设备的各种拓扑可以被设计成“群集”，其中每个群集彼此通信用于访问远程和本地，用于访问输入/输出设备，以及用于维持高速缓存的一致性。

公开(公告)号：US4803622A

公开(公告)日：1989-02-07

申请号：US46633

申请日：1987-05-07

申请人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

IPC分类号： G06F13/14 ,  G06F13/12 ,  G06F13/38 ,  G06F3/00

CPC分类号： G06F13/124

摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.

摘要翻译： 一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。 可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。 服务表包括分成字段的多个条目。 解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。 连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。 连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器 套。 服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。 每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。

公开(公告)号：US4853849A

公开(公告)日：1989-08-01

申请号：US942608

申请日：1986-12-17

申请人： William L. Bain, Jr. ,  Marcos de Oliveira Camargo ,  Robert C. Duzett ,  Artur H. Lederhofer ,  Craig B. Peterson ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  Marcos de Oliveira Camargo ,  Robert C. Duzett ,  Artur H. Lederhofer ,  Craig B. Peterson ,  John L. Wipfli

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F13/12

CPC分类号： G06F13/124 ,  G06F13/126

摘要： An I/O processor includes an execution unit (EU), a register file, an I/O bus sequencer and a local bus sequencer. The EU decodes an ACCESS instruction having a pointer to a parameter register comprised of: a number of fields for storing a sequencer code identifying one of the sequencers; a logical byte specifying a location in memory to be addressed and valid and block bits; a reply register set pointer to a register set in the register file designated to receive a reply to the ACCESS instruction; and, a length field specifying the location and length of a data block in the register file from which data is to be obtained. A data pointer is generated by taking the logical byte in the parameter register and passing it through a register set mapper to produce a register file physical address. The valid bit of the logical byte is turned off as it is translated by the register the mapper so that the bus sequencer can take control over the corresponding register set. The block bit is set upon the condition that the ACCESS instruction attempts to access a register set whose valid bit is not set, and the block bit is reset upon the condition that the task which is executing the ACCESS instruction attempts to access a register set whose block and valid bits are set.

摘要翻译： I / O处理器包括执行单元（EU），寄存器文件，I / O总线排序器和本地总线排序器。 EU解码具有指向参数寄存器的指针的ACCESS指令，该指令包括：用于存储识别其中一个定序器的定序器代码的多个字段; 指定存储器中要被寻址和有效的位置的逻辑字节和块位; 回复寄存器设置指向寄存器文件中设置的寄存器文件的指针，用于接收对ACCESS指令的回复; 以及指定要从其获得数据的寄存器文件中的数据块的位置和长度的长度字段。 通过取参数寄存器中的逻辑字节并通过寄存器集映射器产生寄存器文件物理地址来生成数据指针。 逻辑字节的有效位被关闭，因为它由寄存器转换为映射器，以便总线排序器可以控制相应的寄存器集。 在ACCESS指令尝试访问其有效位未设置的寄存器组的情况下，块位被置位，并且在执行ACCESS指令的任务试图访问其寄存器组的条件下，块位被复位 块和有效位被置位。

公开(公告)号：US4503534A

公开(公告)日：1985-03-05

申请号：US393905

申请日：1982-06-30

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/00

CPC分类号： G06F11/1629 ,  G06F11/0724 ,  G06F11/0763 ,  G06F11/165 ,  G06F11/1666 ,  G06F11/1658 ,  G06F11/1675

摘要： A number of intelligent nodes (bus-interface units-BIUs and memory-control units-MCUs) are provided in a matrix composed of processor buses (105) with corresponding error-reporting and control lines (106); and memory buses (107) with corresponding error-reporting and control lines (108). Each node (100, 101, 102, 103) has means for logging errors and reporting errors on the error-report lines (106, 108). Processor modules (110) and memory modules (112) are each connected to a node which controls access to a common memory bus (107). Each node includes means (a married bit-170 and a shadow bit-172) for marrying modules in pairs such that each module in the pair tracks the operations directed to the module pair, and each module in the pair alternates with the other module in the handling of requests or replies. Each node registers the ID of the other node in a spouse ID register. Comparison logic (162, 164) in each node resets the married bit upon the condition that the node ID (identifying the node at which the error occurred) in an error-report message is equal to the ID stored in the spouse ID register, thus identifying the spouse node (the partner of the node in which the comparison logic is located) as the source of the error. Resetting the married bit splits apart the primary/shadow pair, so that the error-free module takes over and ceases to alternate with its partner.

摘要翻译： 在由具有相应的错误报告和控制线（106）的处理器总线（105）组成的矩阵中提供了许多智能节点（总线接口单元-IBU和存储器控制单元-MCU）。 和具有对应的错误报告和控制线（108）的存储器总线（107）。 每个节点（100,101,102,103）具有用于在错误报告行（106,108）上记录错误和报告错误的装置。 处理器模块（110）和存储器模块（112）各自连接到控制对公共存储器总线（107）的访问的节点。 每个节点包括用于成对结合模块的装置（已婚的位170和影子位172），使得该对中的每个模块跟踪针对模块对的操作，并且该对中的每个模块与另一模块中的每个模块交替 处理请求或回复。 每个节点在配偶ID寄存器中注册另一个节点的ID。 每个节点中的比较逻辑（162,164）在错误报告消息中识别发生错误的节点ID等于配偶ID寄存器中存储的ID的条件下重置已婚比特，因此 识别配偶节点（比较逻辑所在的节点的伙伴）作为错误的来源。 重新设置已拆分的主分割主体/阴影对，使得无错误的模块接管并停止与其伙伴交替使用。

公开(公告)号：US4438494A

公开(公告)日：1984-03-20

申请号：US296025

申请日：1981-08-25

申请人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  Brad W. Hosler ,  David B. Johnson ,  Craig B. Peterson

发明人： David L. Budde ,  David G. Carson ,  Anthony L. Cornish ,  Brad W. Hosler ,  David B. Johnson ,  Craig B. Peterson

IPC分类号： G06F11/20 ,  G06F11/07 ,  G06F11/00

CPC分类号： G06F11/0772 ,  G06F11/0724 ,  G06F11/073 ,  G06F11/0745 ,  G06F11/0784 ,  G06F11/0793

摘要： A number of intelligent crossbar switches (100) are provided in a matrix of orthogonal lines interconnecting processor (110) and memory control unit (MCU) modules (112). The matrix is composed of processor buses (105) and corresponding error-reporting lines (106); and memory buses (107) with corresponding error-reporting lines (108). At the intersection of these lines is a crossbar switch node (100). The crossbar switches function to pass memory requests from a processor to a memory module attached to an MCU node and to pass any data associated with the requests. The system is organized into confinement areas at the boundaries of which are positioned error-detection mechanisms to deal with information flow occurring across area boundaries. Each crossbar switch and MCU node has means for the logging and signaling of errors to other nodes. Means are provided to reconfigure the system to reroute traffic around the confinement area at fault and for restarting system operation in a possibly degraded mode.

摘要翻译： 在互连处理器（110）和存储器控制单元（MCU）模块（112）的正交线的矩阵中提供了许多智能交叉开关（100）。 矩阵由处理器总线（105）和相应的错误报告线（106）组成。 和具有对应的错误报告行（108）的存储器总线（107）。 这些线路的交叉点是交叉开关节点（100）。 交叉开关用于将存储器请求从处理器传递到连接到MCU节点的存储器模块，并传递与请求相关联的任何数据。 系统被组织成限制区域，其边界位于错误检测机制中，以处理跨区域边界发生的信息流。 每个交叉开关和MCU节点都有用于记录和向其他节点发送错误信号的手段。 提供了用于重新配置系统以重新路由处于故障的限制区域周围的业务并且以可能降级的模式重新启动系统操作的手段。

公开(公告)号：US4829425A

公开(公告)日：1989-05-09

申请号：US168635

申请日：1988-03-01

申请人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

IPC分类号： G06F13/40

CPC分类号： G06F13/404

摘要： An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

摘要翻译： 用于控制本地总线和I / O总线之间的数据传输的I / O处理器。 执行单元，I / O总线排序器和本地总线顺控程序连接到寄存器文件。 寄存器文件被均匀地寻址，执行单元，本地总线排序器和I / O总线排序器中的每一个具有对寄存器文件的读/写访问。 寄存器文件由多个寄存器组构成。 执行单元包括编程处理器，其被编程为通过在消息形式的任务之间传递寄存器集描述符来在处理器上运行的任务之间分配寄存器集。 本地总线定序器包括面向分组的多处理器总线，每个分组中存在可变数量的字节。 I / O定序器包括用于在I / O总线和寄存器文件之间以总线相关数据速率对数据进行多字节排序的逻辑。 每个任务包括任务帧，每个任务帧包括寄存器集指针。 寄存器集指针映射在用于访问指针的任务的指令中使用的逻辑地址和用于访问寄存器的物理寄存器集地址之间。 每个执行单元，本地总线排序器和I / O总线顺控程序中的程序逻辑动态地将寄存器组分配给发送和目标任务。