-
公开(公告)号:US20220066898A1
公开(公告)日:2022-03-03
申请号:US17005114
申请日:2020-08-27
Applicant: Micron Technology, Inc.
Inventor: Todd A. Marquart , Niccolo' Righetti , Jeffrey S. McNeil, JR. , Akira Goda , Kishore K. Muchherla , Mark A. Helm , Gil Golov , Jeremy Binfet , Carmine Miccoli , Giuseppina Puzzilli
Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.
-
公开(公告)号:US20220066677A1
公开(公告)日:2022-03-03
申请号:US17001729
申请日:2020-08-25
Applicant: Micron Technology, Inc.
Inventor: Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, JR. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
IPC: G06F3/06
Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.
-
公开(公告)号:US11189355B1
公开(公告)日:2021-11-30
申请号:US17001745
申请日:2020-08-25
Applicant: Micron Technology, Inc.
Inventor: Vamsi Pavan Rayaprolu , Giuseppina Puzzilli , Karl D. Schuh , Jeffrey S. McNeil, Jr. , Kishore K. Muchherla , Ashutosh Malshe , Niccolo' Righetti
Abstract: A first group of memory cells of a memory device can be subjected to a particular quantity of program/erase cycles (PECs) in response to a programming operation performed on a second group of memory cells of the memory device. Subsequent to subjecting the first group of memory cells to the particular quantity of PECs, a data retention capability of the first group of memory cells can be assessed.
-
公开(公告)号:US20130332769A1
公开(公告)日:2013-12-12
申请号:US13970055
申请日:2013-08-19
Applicant: Micron Technology, Inc.
Inventor: Krishna K. Parat , Akira Goda , Koichi Kawai , Brian J. Soderling , Jeremy Binfet , Arnaud A. Furnemont , Tejas Krishnamohan , Tyson M. Stichka , Giuseppina Puzzilli
IPC: G11C29/00
CPC classification number: G11C29/765 , G11C11/5628 , G11C16/0483 , G11C16/16 , G11C16/349 , G11C29/789
Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.
Abstract translation: 公开了存储器件和方法,包括涉及擦除存储器单元块的方法。 在擦除块之后,并且在块的后续编程之前,基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值,则该块将从使用中退出。 公开了另外的实施例。
-
-
-