公开(公告)号：US20220216864A1

公开(公告)日：2022-07-07

申请号：US17656397

申请日：2022-03-24

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Yuan He ,  Toru Ishikawa

IPC: H03K17/16 ,  G06F13/40 ,  G11C7/10

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods are disclosed. An apparatus includes a first output terminal electrically connected to a pull-up gate terminal of at least one pull-up SCRC transistor and a second output terminal electrically connected to a pull-down gate terminal of at least one pull-down SCRC transistor. The apparatus also includes a first resistive path between a first input terminal and the first output terminal and a second resistive path between the second input terminal and the second output terminal. The apparatus further includes a charge transfer gate electrically connected between the first resistive path and the second resistive path.

公开(公告)号：US11380387B1

公开(公告)日：2022-07-05

申请号：US17209650

申请日：2021-03-23

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Tae H. Kim

IPC: G11C7/00 ,  G11C11/4091 ,  G11C7/10 ,  H01L27/06 ,  H01L27/108

Abstract: A memory device can comprise an arrays of memory cells comprising a plurality of vertically stacked tiers of memory cells, a respective plurality of horizontal access lines coupled to each of the plurality of tiers of memory cells, and a plurality of vertical sense lines coupled to each of the plurality of tiers of memory cells. The array of memory cells can further comprise a plurality of multiplexors each coupled to a respective vertical sense line, wherein each of the plurality of multiplexors includes a first portion and a second portion, the first portion is coupled to the array of memory cells and the second portion is formed on a substrate material. The array of memory cells can further comprise a semiconductor under the array (SuA) circuitry comprising a plurality of sense amplifiers, each sense amplifier coupled to a respective subset of the plurality of multiplexors.

公开(公告)号：US20220164251A1

公开(公告)日：2022-05-26

申请号：US17100775

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Jiyun Li

IPC: G06F11/10 ,  G06K9/62 ,  G06F1/12 ,  G06F1/10

Abstract: Methods, apparatuses, and systems related to an apparatus are described. The apparatus may include (1) a fuse array configured to provide non-volatile storage of fuse data and (2) local latches configured to store the fuse data during runtime of the apparatus. The apparatus may further include an error processing circuit configured to determine error detection-correction data for the fuse data. The apparatus may subsequently broadcast data stored in the local latches to the error processing circuit to determine, using the error detection-correction data, whether the locally latched data has been corrupted. The error processing circuit may generate corrected data to replace the locally latched data based on determining corruption in the locally latched data.

公开(公告)号：US20220139444A1

公开(公告)日：2022-05-05

申请号：US17084250

申请日：2020-10-29

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Hiroshi Akamatsu

IPC: G11C11/408 ,  G11C11/4091 ,  G11C11/4074 ,  G11C11/406 ,  G11C8/18

Abstract: A memory mat architecture is presented where a column decoder is disposed within the memory array. The location of the column decoder reduces a distance between the column decoder and a target memory cell and thus reduces a distance that a column select signal travels from the column decoder to the target memory cell. A single predecoder is disposed in a bank controller for the memory array. The column decoder may be disposed in the middle of the memory array or offset from the middle near the far edge of the memory array opposite the bank controller. The location of the column decoder enables a reduced array access time to obtain data from the target memory cell.

公开(公告)号：US11290103B1

公开(公告)日：2022-03-29

申请号：US16953457

申请日：2020-11-20

Applicant: Micron Technology, Inc.

Inventor： Hiroshi Akamatsu ,  Yuan He ,  Toru Ishikawa

IPC: G06F13/40 ,  H03K17/16 ,  G11C7/10

Abstract: Charge transfer between gate terminals of sub-threshold current reduction circuit (SCRC) transistors and related apparatuses and methods is disclosed. An apparatus includes a pull-up SCRC transistor, a pull-down SCRC transistor, and a charge transfer circuit. The pull-up SCRC transistor includes a pull-up gate terminal. The pull-down SCRC transistor includes a pull-down gate terminal. The charge transfer circuit is electrically connected between the pull-up gate terminal and the pull-down gate terminal. The charge transfer circuit is configured to transfer charge between the pull-up gate terminal and the pull-down gate terminal.

公开(公告)号：US11250903B2

公开(公告)日：2022-02-15

申请号：US16811738

申请日：2020-03-06

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Chikara Kondo ,  Daigo Toyama

IPC: G11C11/4074 ,  G11C5/14 ,  G11C11/4096 ,  G11C11/4093 ,  G11C11/406

Abstract: Disclosed herein is an apparatus that includes a first semiconductor chip including a memory cell array having a volatile memory cell and an access control circuit configured to perform a refresh operation on the volatile memory cell, and a second semiconductor chip including a power generator configured to supply a first power supply voltage to the first semiconductor chip. The access control circuit is configured to activate a first enable signal during the refresh operation. The second semiconductor chip is configured to change a capability of the power generator based on the first enable signal.

公开(公告)号：US11217297B2

公开(公告)日：2022-01-04

申请号：US17001291

申请日：2020-08-24

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Yutaka Ito

IPC: G11C11/406 ,  G11C11/408

Abstract: Methods, systems, and devices for techniques for reducing row hammer refresh are described. A memory device may be segmented into regions based on bits (e.g., the least significant bits) of row addresses such that consecutive word lines belong to different regions. A memory device may initiate a refresh operation for a first row of memory cells corresponding to a first word line. The memory device may determine that the first row is an aggressor row of a row hammer attack and may determine an adjacent row associated with a second word line as a victim row that may need to be refreshed (e.g., to counteract potential data corruption due to a row hammer attack). The memory die may determine whether to perform a row-hammer refresh operation on the victim row based on whether the victim row belongs to a region that is masked.

公开(公告)号：US20210264966A1

公开(公告)日：2021-08-26

申请号：US16802306

申请日：2020-02-26

Applicant: Micron Technology, Inc.

Inventor： Yuan He ,  Sang-Kyun Park

IPC: G11C11/4091 ,  G11C11/4094 ,  H01L27/108

Abstract: Methods, apparatuses, and systems related to a memory device are described. The memory device may include a sense amplifier with a sensing circuit configured to precharge a connected extended digit line. A balancing circuit may be connected to the extended digit line opposite the sensing circuit. The balancing circuit may be configured to selectively connect the extended digit line to a precharging source to precharge the extended digit line.

公开(公告)号：US20210249066A1

公开(公告)日：2021-08-12

申请号：US16785179

申请日：2020-02-07

Applicant: Micron Technology, Inc.

Inventor： Yuan He

IPC: G11C11/4091 ,  H01L27/108 ,  G11C11/4074

Abstract: An edge memory array mat with access lines that are split in half, and a bank of sense amplifiers formed in a region that separates the access line segment halves extending perpendicular to the access line segments. The sense amplifiers of the bank of sense amplifiers are coupled to opposing ends of a first subset of the half access lines pairs. The edge memory array mat further includes digit line (DL) jumpers or another structure configured to connect a second subset of the half access line pairs across the region occupied by the bank of sense amplifiers to form combined or extended access lines that extend to a bank of sense amplifiers coupled between the edge memory array mat and an inner memory array mat.

公开(公告)号：US11081160B2

公开(公告)日：2021-08-03

申请号：US16783063

申请日：2020-02-05

Applicant: c/o Micron Technology, Inc.

Inventor： Yutaka Ito ,  Yuan He

IPC: G11C8/00 ,  G11C11/406 ,  G11C11/408 ,  G11C11/4076

Abstract: Apparatuses and methods for triggering row hammer address sampling are described. An example apparatus includes an oscillator circuit configured to provide a clock signal, and a filter circuit. The filter circuit includes a control circuit configured to receive pulses of the clock signal and provide an output signal that represents a count number by counting a number of pulses of the clock signal and control a probability of enabling the output signal based on the count number. The filter circuit further includes a logic gate configured to pass one of the pulses of the clock signal responsive to the output signal from the control circuit being enabled and filter another of the pulses responsive to the output signal from the control circuit being not enabled.