公开(公告)号：US20240172432A1

公开(公告)日：2024-05-23

申请号：US18428325

申请日：2024-01-31

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Durai Vishak Nirmal Ramaswamy ,  Yunfei Gao ,  Sanh D. Tang ,  Deepak Chandra Pandey

IPC: H10B41/27 ,  G11C5/02 ,  G11C5/06 ,  H10B43/27

CPC classification number: H10B41/27 ,  G11C5/025 ,  G11C5/06 ,  H10B43/27

Abstract: Some embodiments include an integrated assembly having a carrier-sink-structure, and having digit lines over the carrier-sink-structure. Transistor body regions are over the digit lines. Extensions extend from the carrier-sink-structure to the transistor body regions. The extensions are configured to drain excess carriers from the transistor body regions. Lower source/drain regions are between the transistor body regions and the digit lines, and are coupled with the digit lines. Upper source/drain regions are over the transistor body regions, and are coupled with storage elements. Gates are adjacent the transistor body regions. The transistor body regions, lower source/drain regions and upper source/drain regions are together comprised a plurality of transistors. The transistors and the storage elements are together comprised by a plurality of memory cells of a memory array. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11515311B2

公开(公告)日：2022-11-29

申请号：US16711531

申请日：2019-12-12

Applicant: Micron Technology, Inc.

Inventor： Venkata Naveen Kumar Neelapala ,  Deepak Chandra Pandey ,  Naveen Kaushik

IPC: H01L27/108 ,  H01L29/423

Abstract: Systems, apparatuses, and methods related to semiconductor structure formation are described. An example apparatus includes a first trench and a second trench formed in a semiconductor substrate material, where the first and second trenches are adjacent and separated by the semiconductor substrate material. The apparatus includes a metallic material formed to a first height in the first trench that is less than, relative to the semiconductor substrate material, a second height of the metallic material formed in the second trench and a polysilicon material formed over the metallic material in the first trench to a first depth greater than, relative to the semiconductor substrate material, a second depth of the polysilicon material formed over the metallic material in the second trench. The greater first depth of the polysilicon material formed in the first trench reduces transfer of charge by way of the metallic material in the first trench.

公开(公告)号：US11430793B2

公开(公告)日：2022-08-30

申请号：US16899339

申请日：2020-06-11

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Venkata Naveen Kumar Neelapala ,  Haitao Liu

IPC: H01L27/108

Abstract: A microelectronic device comprises a first pillar of a semiconductive material, a second pillar of the semiconductive material adjacent to the first pillar of the semiconductive material, an active word line extending between the first pillar and the second pillar, and a passing word line extending on a side of the second pillar opposite the active word line, the passing word line extending into an isolation region within the semiconductive material, the isolation region comprising a lower portion and an upper portion having a substantially circular cross-sectional shape and a larger lateral dimension than the lower portion. Related microelectronic devices, electronic systems, and methods are also described.

公开(公告)号：US11373913B2

公开(公告)日：2022-06-28

申请号：US16558928

申请日：2019-09-03

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Haitao Liu ,  Kamal M. Karda

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11507 ,  H01L23/528 ,  H01L29/786 ,  H01L29/792 ,  H01L27/24 ,  H01L21/8239 ,  H01L27/108 ,  H01L21/768 ,  H01L21/311

Abstract: An array of vertical transistors comprises spaced pillars individually comprising a channel region of individual vertical transistors. A horizontally-elongated conductor line directly electrically couples together individual of the channel regions of the pillars of a plurality of the vertical transistors. An upper source/drain region is above the individual channel regions of the pillars, a lower source/drain region is below the individual channel regions of the pillars, and a conductive gate line is operatively aside the individual channel regions of the pillars and that interconnects multiple of the vertical transistors. Methods are disclosed.

公开(公告)号：US11177265B2

公开(公告)日：2021-11-16

申请号：US16862122

申请日：2020-04-29

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Si-Woo Lee ,  Haitao Liu ,  Deepak Chandra Pandey

IPC: H01L27/108 ,  H01L29/10 ,  H01L29/49 ,  H01L29/167

Abstract: Some embodiments include an integrated assembly having an active-region-pillar extending upwardly from a base. The active-region-pillar includes a digit-line-contact-region between a first storage-element-contact-region and a second storage-element-contact-region. A threshold-voltage-inducing-structure is adjacent a lower portion of the active-region-pillar. A first channel region includes a first portion of the active-region-pillar between the digit-line-contact-region and the first storage-element-contact-region. A second channel region includes a second portion of the active-region-pillar between the digit-line-contact-region and the second storage-element-contact-region. A first wordline is adjacent the first portion of the active-region-pillar. A second wordline is adjacent the second portion of the active-region-pillar. A digit-line is coupled with the digit-line-contact-region. First and second storage-elements are coupled with the first and second storage-element-contact-regions. A voltage source is coupled with the threshold-voltage-inducing-structure to electrostatically induce a desired threshold voltage along the first and second channel regions.

公开(公告)号：US11171206B2

公开(公告)日：2021-11-09

申请号：US16509093

申请日：2019-07-11

Applicant: Micron Technology, Inc.

Inventor： Kamal M. Karda ,  Haitao Liu ,  Si-Woo Lee ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey ,  Chandra V. Mouli ,  John A. Smythe, III

IPC: H01L29/06 ,  H01L27/108 ,  H01L21/762

Abstract: An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

公开(公告)号：US20210174840A1

公开(公告)日：2021-06-10

申请号：US16709030

申请日：2019-12-10

Applicant: Micron Technology, Inc.

Inventor： Naveen Kaushik ,  Fatma Arzum Simsek-Ege ,  Deepak Chandra Pandey

IPC: G11C5/06 ,  H01L27/108

Abstract: Some embodiments include an integrated assembly having a memory array, and having digit lines extending along a first direction through the memory array. Insulative spacers are along sidewalls of the digit lines. The insulative spacers extend continuously along the digit lines through the memory array. Conductive regions are laterally spaced from the digit lines by intervening regions. The conductive regions are configured as segments spaced apart from one another along the first direction. The intervening regions include regions of the insulative spacers and include void regions adjacent the regions of the insulative spacers. The void regions are configured as void-region-segments which are spaced apart from one another along the first direction by insulative structures. Storage-elements are associated with the conductive regions. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US11018255B2

公开(公告)日：2021-05-25

申请号：US16110217

申请日：2018-08-23

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Guangyu Huang ,  Chandra V. Mouli ,  Akira Goda ,  Deepak Chandra Pandey ,  Kamal M. Karda

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/423 ,  H01L29/267 ,  H01L27/11556 ,  H01L29/66 ,  H01L21/02 ,  H01L21/44 ,  H01L27/11582 ,  H01L29/08 ,  H01L21/425 ,  H01L29/10 ,  H01L29/786 ,  H01L27/1157 ,  H01L29/36 ,  H01L29/49 ,  H01L29/417

Abstract: A device includes a string driver comprising a channel region between a drain region and a source region. At least one of the channel region, the drain region, and the source region comprises a high band gap material. A gate region is adjacent and spaced from the high band gap material. The string driver is configured for high-voltage operation in association with an array of charge storage devices (e.g., 2D NAND or 3D NAND). Additional devices and systems (e.g., non-volatile memory systems) including the string drivers are disclosed, as are methods of forming the string drivers.

公开(公告)号：US20200105311A1

公开(公告)日：2020-04-02

申请号：US16702926

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Deepak Chandra Pandey ,  Si-Woo Lee

IPC: G11C5/10 ,  H01L27/108 ,  G11C11/401

Abstract: Some embodiments include an integrated assembly which has digit-line-contact-regions laterally spaced from one another by intervening regions. Non-conductive-semiconductor-material is over the intervening regions. Openings extend through the non-conductive-semiconductor-material to the digit-line-contact-regions. Conductive-semiconductor-material-interconnects are within the openings and are coupled with the digit-line-contact-regions. Upper surfaces of the conductive-semiconductor-material-interconnects are beneath a lower surface of the non-conductive-semiconductor-material. Metal-containing-digit-lines are over the non-conductive-semiconductor-material. Conductive regions extend downwardly from the metal-containing-digit-lines to couple with the conductive-semiconductor-material-interconnects. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20190252553A1

公开(公告)日：2019-08-15

申请号：US16132879

申请日：2018-09-17

Applicant: Micron Technology, Inc.

Inventor： Haitao Liu ,  Yunfei Gao ,  Kamal M. Karda ,  Deepak Chandra Pandey ,  Sanh D. Tang ,  Litao Yang

IPC: H01L29/786 ,  H01L29/78 ,  H01L27/088

Abstract: Systems, apparatuses and methods related to access devices formed with conductive contacts are described. An example apparatus may include an access device that includes a field-effect transistor (FET). A vertical pillar may be formed to include a channel of the FET, with a portion of the vertical pillar formed between at least two gates of the FET (i.e., a multi-gate Fin-FET). A conductive contact may be coupled to a body region of the vertical pillar.