公开(公告)号：US10366970B2

公开(公告)日：2019-07-30

申请号：US16024911

申请日：2018-07-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/48 ,  H01L27/06 ,  H01L27/088 ,  H01L23/522 ,  H01L23/367 ,  H01L21/822 ,  H01L27/092 ,  H01L21/8234

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

公开(公告)号：US20180331073A1

公开(公告)日：2018-11-15

申请号：US16024911

申请日：2018-07-02

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L27/092 ,  H01L27/088 ,  H01L21/8234 ,  H01L27/06 ,  H01L23/522

CPC classification number: H01L25/0657 ,  H01L21/8221 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device comprising: a first single crystal layer comprising a plurality of first transistors; at least one metal layer interconnecting said first transistors, a portion of said first transistors forming a plurality of logic gates; a plurality of second transistors overlaying said first single crystal layer; a plurality of third transistors overlaying said plurality of second transistors; a top metal layer overlying said third transistors; first circuits underlying said first single crystal layer; second circuits overlying said top metal layer; a first set of connections underlying said at least one metal layer, wherein said first set of connections connects said first transistors to said first circuits; a second set of connections overlying said top metal layer, wherein said second set of connections connects said first transistors to said second circuits, and wherein said first set of connections comprises a through silicon via (TSV).

公开(公告)号：US20180190619A1

公开(公告)日：2018-07-05

申请号：US15904377

申请日：2018-02-25

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L23/367 ,  H01L27/092 ,  H01L21/8234 ,  H01L27/088 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00 ,  H01L2924/0002

Abstract: A 3D semiconductor device, the device including: a first single crystal layer including a plurality of first transistors; at least one metal layer interconnecting the first transistors, a portion of the first transistors forming a plurality of logic gates; a plurality of second transistors overlaying the first single crystal layer; at least one connection from the plurality of first transistors to a plurality of through silicon vias (TSVs); a plurality of third transistors overlaying the plurality of second transistors, where the plurality of second transistors are self-aligned to the plurality of third transistors having been processed following the same lithography step; and a first memory array and a second memory array, where the first memory array includes the plurality of second transistors and the second memory array includes the plurality of third transistors.

公开(公告)号：US09613887B2

公开(公告)日：2017-04-04

申请号：US15079017

申请日：2016-03-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

公开(公告)号：US09385058B1

公开(公告)日：2016-07-05

申请号：US13803437

申请日：2013-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/70 ,  H01L27/12 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one metal layer; and a second layer including second electronic circuits and a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; the second layer includes a through layer via with a diameter of less than 150 nm; a portion of the first electronic circuits is circumscribed by a first dice lane, and there are no conductive connections to the portion of the first electronic circuits that cross the first dice lane; wherein a portion of the second electronic circuits is circumscribed by a second dice lane, and there are no conductive connections to the portion of the second electronic circuits that cross the second dice lane, and the second dice lane is overlaying and aligned to the first dice lane.

Abstract translation: 一种集成电路装置，包括：基底晶片，包括第一电子电路和多个第一单晶晶体管; 至少一个金属层; 以及包括第二电子电路和多个第二单晶体晶体管的第二层，所述第二层覆盖所述至少一个金属层; 第二层包括直径小于150nm的贯通层通孔; 第一电子电路的一部分由第一骰子通道限定，并且不与第一电子电路的穿过第一骰子通道的部分的导电连接; 其中所述第二电子电路的一部分由第二骰子通道限定，并且没有与所述第二电子电路的穿过所述第二骰子通道的所述部分的导电连接，并且所述第二骰子通道覆盖并对齐到所述第一骰子 车道。

公开(公告)号：US20150311142A1

公开(公告)日：2015-10-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US08803206B1

公开(公告)日：2014-08-12

申请号：US13855786

申请日：2013-04-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Abstract translation: 一种3D半导体器件，包括：第一层，包括第一晶体管; 包括第二晶体管的第二层; 其中第二晶体管与第一晶体管对准，以及第一电路，其包括第一晶体管中的至少一个，其中第一电路具有连接到至少一个第二晶体管的第一电路输出，并且其中至少一个 第二晶体管连接到器件输出，并且其中器件输出包括用于连接到外部器件的接触端口，并且其中第二晶体管中的至少一个基本上大于第一晶体管中的至少一个。

公开(公告)号：US08742476B1

公开(公告)日：2014-06-03

申请号：US13685751

申请日：2012-11-27

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L21/336 ,  H01L21/477

CPC classification number: H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract translation: 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上并且包括铜或铝; 和覆盖在金属层上的第二层; 第二层包括第二晶体管，其包括单晶并且与第一对准标记对准，具有小于40nm的对准误差，单晶包括相对于彼此水平取向的第一区域和第二区域， 区域具有与第二区域基本上不同的掺杂剂浓度。

公开(公告)号：US20140145272A1

公开(公告)日：2014-05-29

申请号：US13685751

申请日：2012-11-27

Applicant: MONOLITHIC 3D INC.

Inventor： Zvi Or-Bach ,  Deepak Sekar ,  Brian Cronquist

IPC: H01L23/544 ,  H01L27/092 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device including: a first single crystal layer including first transistors, first alignment mark, and at least one metal layer, the at least one metal layer overlying the first single crystal layer and includes copper or aluminum; and a second layer overlying the metal layer; the second layer includes second transistors which include mono-crystal and are aligned to the first alignment mark with less than 40 nm alignment error, the mono-crystal includes a first region and second region which are horizontally oriented with respect to each other, the first region has substantially different dopant concentration than the second region.

Abstract translation: 一种半导体器件，包括：第一单晶层，包括第一晶体管，第一对准标记和至少一个金属层，所述至少一个金属层覆盖在所述第一单晶层上并且包括铜或铝; 和覆盖在金属层上的第二层; 第二层包括第二晶体管，其包括单晶并且与第一对准标记对准，具有小于40nm的对准误差，单晶包括相对于彼此水平取向的第一区域和第二区域， 区域具有与第二区域基本上不同的掺杂剂浓度。