公开(公告)号：US07729884B2

公开(公告)日：2010-06-01

申请号：US11267221

申请日：2005-11-04

申请人： Yu Huang ,  Wu-Tung Cheng ,  Janusz Rajski

发明人： Yu Huang ,  Wu-Tung Cheng ,  Janusz Rajski

IPC分类号： G06F11/30 ,  G06F11/00

CPC分类号： G01R31/318547 ,  G06F11/267 ,  G06F11/27

摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received including entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

摘要翻译： 本文公开了用于执行故障诊断的方法，装置和系统。 在一个示例性实施例中，接收到故障日志，包括指示针对链图案的压缩测试响应的条目和对扫描模式的压缩测试响应。 至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。 至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。 可以报​​告一个或多个识别的扫描单元候选。 还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。 同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

公开(公告)号：US07716548B2

公开(公告)日：2010-05-11

申请号：US12215593

申请日：2008-06-27

申请人： Wu-Tung Cheng ,  Manish Sharma

发明人： Wu-Tung Cheng ,  Manish Sharma

IPC分类号： G01R31/28

CPC分类号： G01R31/31703 ,  G01R31/318547

摘要： Methods, apparatus, and systems for filtering compacted test responses are disclosed. The methods, apparatus, and systems can be used, for example, to remove the effects of unknown test values. For instance, in one embodiment, a compacted test response from a compactor of a circuit-under-test is received. In this embodiment, the compacted test response includes one or more compacted test response values that are dependent on one or more respective unknown values. The compacted test response is filtered to remove the dependency of at least some of the compacted test response values on the one or more respective unknown values, and a filtered test response is output. Various filtering circuits and testing systems are also disclosed.

摘要翻译： 公开了用于过滤压实测试响应的方法，装置和系统。 可以使用方法，装置和系统来例如去除未知测试值的影响。 例如，在一个实施例中，接收来自被测电路的压实机的压实测试响应。 在该实施例中，压实的测试响应包括依赖于一个或多个相应未知值的一个或多个压缩测试响应值。 过滤压实的测试响应以去除至少一些压实的测试响应值对一个或多个相应的未知值的依赖性，并且输出经滤波的测试响应。 还公开了各种滤波电路和测试系统。

公开(公告)号：US20090254786A1

公开(公告)日：2009-10-08

申请号：US12265693

申请日：2008-11-05

申请人： Wu-Tung Cheng ,  Grzegorz Mrugalski

发明人： Wu-Tung Cheng ,  Grzegorz Mrugalski

IPC分类号： G01R31/3177 ,  G06F11/25

CPC分类号： G01R31/31813 ,  G01R31/318371 ,  G01R31/318547

摘要： X-masking registers are added in front of a compactor in test data compression environment to remove unknown values. The X-masking registers block out some chains due to unknown values and select other chains to feed the compactor. This X-masking capability is used to select one scan cell to observe at a time after a failure is observed at the compactor output.

摘要翻译： 在测试数据压缩环境中，将X-masking寄存器添加到压实器的前面，以去除未知值。 X屏蔽寄存器由于未知值而阻塞一些链，并选择其他链来馈送压实机。 该X掩蔽功能用于选择一个扫描单元，以便在压实机输出上观察到故障后一次观察。

公开(公告)号：US07424660B2

公开(公告)日：2008-09-09

申请号：US11397822

申请日：2006-04-03

申请人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

发明人： Omar Kebichi ,  Wu-Tung Cheng ,  Christopher John Hill ,  Paul J. Reuter ,  Yahya M. Z. Mustafa

IPC分类号： G01R31/28 ,  G06F11/00

CPC分类号： G11C29/12015 ,  G11C29/14 ,  G11C29/56012 ,  G11C2029/0401 ,  G11C2029/2602

摘要： A circuit is disclosed for testing memories using multiple built-in self test (BIST) controllers embedded in an integrated circuit (IC). The BIST controllers are brought to a synchronization point during the memory test by allowing for a synchronization state. An output signal from an output pin on the IC indicates the existence of a synchronization state to automated test equipment (ATE). After an ATE receives the output signal, it issues a resume signal through an IC input pin that causes the controllers to advance out of the synchronization state. The ATE controls the synchronization state length by delaying the resume signal. Synchronization states can be used in parametric test algorithms, such as for retention and IDDQ tests. Synchronization states can be incorporated into user-defined algorithms by software design tools that generate an HDL description of a BIST controller operable to apply the algorithm with the synchronization state.

摘要翻译： 公开了一种用于使用嵌入在集成电路（IC）中的多个内置自测（BIST）控制器测试存储器的电路。 通过允许同步状态，BIST控制器在存储器测试期间被带到同步点。 来自IC上的输出引脚的输出信号表示存在与自动测试设备（ATE）的同步状态。 ATE接收到输出信号后，通过IC输入引脚发出一个恢复信号，导致控制器进入同步状态。 ATE通过延迟恢复信号来控制同步状态长度。 同步状态可用于参数化测试算法，例如保留和IDDQ测试。 可以通过软件设计工具将同步状态并入用户定义的算法，该工具可生成可操作以将同步状态应用于算法的BIST控制器的HDL描述。

公开(公告)号：US20080111558A1

公开(公告)日：2008-05-15

申请号：US11876430

申请日：2007-10-22

申请人： Manish Sharma ,  Wu-Tung Cheng

发明人： Manish Sharma ,  Wu-Tung Cheng

IPC分类号： G01R31/02

CPC分类号： G01R31/318569 ,  G01R31/2846

摘要： Among the various embodiments described is a method of detecting defects in a cell of an integrated circuit that analyzes exercising conditions applied to an input of the cell during a capture phase of testing with failed test patterns that produce an indication of a fault and that analyzes the exercising conditions that are applied during a capture phase of testing with observable passing patterns that do not provide an indication of a fault. From the analysis, true failing excitation conditions and passing excitation conditions can be determined and used to identify whether a defect is in the cell or on an interconnect wire of the integrated circuit.

摘要翻译： 所描述的各种实施例中的一种检测集成电路的单元中的缺陷的方法，其分析在测试的捕获阶段期间施加到单元的输入的运行条件，其中产生故障指示的失败的测试图案，并且分析 运行在测试捕获阶段期间应用的条件，其中可观察到的通过模式不提供故障指示。 从分析可以确定真实故障激励条件和通过激励条件，并用于识别缺陷是在集成电路的单元还是互连线上。

公开(公告)号：US20070234157A1

公开(公告)日：2007-10-04

申请号：US11709071

申请日：2007-02-20

申请人： Janusz Rajski ,  Jerzy Tyszer ,  Grzegorz Mrugalski ,  Mark Kassab ,  Wu-Tung Cheng

发明人： Janusz Rajski ,  Jerzy Tyszer ,  Grzegorz Mrugalski ,  Mark Kassab ,  Wu-Tung Cheng

IPC分类号： G01R31/28

CPC分类号： G01R31/3177 ,  G01R31/2851 ,  G01R31/31723 ,  G01R31/31727 ,  G01R31/318547 ,  G01R31/318563 ,  G01R31/318566

摘要： Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

摘要翻译： 这里公开了所谓的“X-press”测试响应压实机的示例性实施例。 所公开的压实机的某些实施例包括过驱动部分和扫描链选择逻辑。 所公开技术的某些实施例提供约1000x的压实比。 所公开的压实机的示例性实施例可以保持与传统的基于扫描的测试场景相同的覆盖范围和大约相同的诊断分辨率。 扫描链选择方案的一些实施例可以显着地减少或完全消除在进入压实机的测试响应中发生的未知状态。 本文还公开了片上比较器电路和用于产生用于屏蔽选择电路的控制电路的方法的实施例。

公开(公告)号：US07200786B2

公开(公告)日：2007-04-03

申请号：US10749283

申请日：2003-12-30

申请人： Wu-Tung Cheng ,  Joseph Rayhawk ,  Xiaogang Du

发明人： Wu-Tung Cheng ,  Joseph Rayhawk ,  Xiaogang Du

IPC分类号： G01R31/28 ,  G11C29/00 ,  G06F11/00 ,  G06F17/50

CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C2029/0401

摘要： Methods and apparatus for analyzing memory defects in an embedded memory are described. According to certain embodiments, the analysis can be performed “at-speed” and can be used to analyze multi-bit failures in words of a word-oriented memory. According to some embodiments, the analysis comprises updating a record of column defects not repaired by spare rows as the memory is being tested. The record can be evaluated after a test to determine whether a repair strategy can successfully repair a memory-under-test.

摘要翻译： 描述了用于分析嵌入式存储器中的存储器缺陷的方法和装置。 根据某些实施例，可以“速度”地执行分析，并且可以用于分析面向字的存储器的单词中的多位故障。 根据一些实施例，分析包括当正在测试存储器时更新未被备用行修复的列缺陷的记录。 测试后可以评估该记录，以确定修复策略是否可以成功修复被测内存。

公开(公告)号：US20060111873A1

公开(公告)日：2006-05-25

申请号：US11267221

申请日：2005-11-04

申请人： Yu Huang ,  Wu-Tung Cheng ,  Janusz Rajski

发明人： Yu Huang ,  Wu-Tung Cheng ,  Janusz Rajski

IPC分类号： G21C17/00

CPC分类号： G01R31/318547 ,  G06F11/267 ,  G06F11/27

摘要： Methods, apparatus, and systems for performing fault diagnosis are disclosed herein. In one exemplary embodiment, a failure log is received comprising entries indicative of compressed test responses to chain patterns and compressed test responses to scan patterns. A faulty scan chain in the circuit-under-test is identified based at least in part on one or more of the entries indicative of the compressed test responses to chain patterns. One or more faulty scan cell candidates in the faulty scan chain are identified based at least in part on one or more of the entries indicative of the compressed test responses to scan patterns. The one or more identified scan cell candidates can be reported. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods are also provided. Likewise, computer-readable media storing lists of fault candidates identified by any of the disclosed methods are also provided.

摘要翻译： 本文公开了用于执行故障诊断的方法，装置和系统。 在一个示例性实施例中，接收到故障日志，其包括指示对链模式的压缩测试响应的条目和对扫描模式的压缩测试响应。 至少部分地基于指示压缩的测试对链模式的测试响应的一个或多个条目来识别被测电路中的有缺陷的扫描链。 至少部分地基于指示对扫描模式的压缩测试响应的一个或多个条目来识别故障扫描链中的一个或多个错误的扫描小区候选。 可以报​​告一个或多个识别的扫描单元候选。 还提供了包括用于使计算机执行任何所公开的方法的计算机可执行指令的计算机可读介质。 同样，还提供了存储通过任何所公开的方法识别的故障候选列表的计算机可读介质。

公开(公告)号：US20050081130A1

公开(公告)日：2005-04-14

申请号：US10961760

申请日：2004-10-07

申请人： Thomas Rinderknecht ,  Wu-Tung Cheng

发明人： Thomas Rinderknecht ,  Wu-Tung Cheng

IPC分类号： G01R31/3185 ,  G01R31/28

CPC分类号： G01R31/318547

摘要： Various new and non-obvious apparatus and methods for testing an integrated circuit are disclosed. In one exemplary embodiment, a control point is selected in an integrated circuit design. Scan cells in the integrated circuit design are identified that can be loaded with a set of fixed values in order to propagate a desired test value to the control point. The integrated circuit design is modified to include circuit components configured to load the scan cells in the integrated circuit design with the set of fixed values during a test phase. The one or more scan cells may be identified by justifying the control point to the scan cells, thereby determining values that the scan cells must output in order to drive the control point to the desired test value. Computer-readable media comprising computer-executable instructions for causing a computer to perform any of the disclosed methods or computer-readable design information for any of the disclosed apparatus are also disclosed.

摘要翻译： 公开了用于测试集成电路的各种新的和非显而易见的装置和方法。 在一个示例性实施例中，在集成电路设计中选择控制点。 识别集成电路设计中的扫描单元，其可以加载一组固定值，以将期望的测试值传播到控制点。 集成电路设计被修改为包括配置成在测试阶段期间以集合的固定值在集成电路设计中加载扫描单元的电路组件。 可以通过将控制点对准扫描单元来识别一个或多个扫描单元，从而确定扫描单元必须输出的值，以便将控制点驱动到期望的测试值。 还公开了包括计算机可执行指令的计算机可读介质，所述计算机可执行指令用于使计算机执行任何所公开的方法或任何所公开的设备的计算机可读设计信息。

公开(公告)号：US08862956B2

公开(公告)日：2014-10-14

申请号：US13397594

申请日：2012-02-15

申请人： Yu Huang ,  Wu-Tung Cheng ,  Ting-Pu Tai ,  Liyang Lai ,  Ruifeng Guo

发明人： Yu Huang ,  Wu-Tung Cheng ,  Ting-Pu Tai ,  Liyang Lai ,  Ruifeng Guo

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/267 ,  G01R31/3177 ,  G06F11/27

CPC分类号： G01R31/318594 ,  G01R31/3177 ,  G01R31/318541 ,  G06F11/267 ,  G06F11/27

摘要： Aspects of the invention relate to techniques for diagnosing compound hold-time faults. A profiling-based scan chain diagnosis may be performed on a faulty scan chain to determine observed scan cell failing probability information and one or more faulty segments based on scan pattern test information. Calculated scan cell failing probability information may then be derived. Based on the calculated scan cell failing probability information and the observed scan cell failing probability information, one or more validated faulty segments are verified to have one or more compound hold-time faults. Finally, one or more clock defect suspects may be identified based on information of the one or more validated faulty segments.

摘要翻译： 本发明的方面涉及用于诊断复合保持时间故障的技术。 可以在故障扫描链上执行基于分析的扫描链诊断，以基于扫描模式测试信息来确定观察到的扫描单元故障概率信息和一个或多个故障段。 然后可以导出计算的扫描单元故障概率信息。 基于计算的扫描单元故障概率信息和观察到的扫描单元故障概率信息，验证一个或多个经验证的故障段具有一个或多个复合保持时间故障。 最后，可以基于一个或多个经验证的故障段的信息来识别一个或多个时钟缺陷嫌疑犯。