公开(公告)号：US20210337185A1

公开(公告)日：2021-10-28

申请号：US17368123

申请日：2021-07-06

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Yusuke KATO

IPC: H04N19/105 ,  H04N19/176 ,  H04N19/182

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry, in operation: derives, as a first parameter, a total sum of absolute values of sums of horizontal gradient values respectively for pairs of relative pixel positions; derives, as a second parameter, a total sum of absolute values of sums of vertical gradient values respectively for the pairs of relative pixel positions; derives, as a third parameter, a total sum of horizontal-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fourth parameter, a total sum of vertical-related pixel difference values respectively for the pairs of relative pixel positions; derives, as a fifth parameter, a total sum of vertical-related sums of horizontal gradient values respectively for the pairs of relative pixel positions; and generates a prediction image to be used to encode the current block using the first, second, third, fourth, and fifth parameters.

公开(公告)号：US20210327100A1

公开(公告)日：2021-10-21

申请号：US17365243

申请日：2021-07-01

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Toshiyasu SUGIO ,  Takahiro NISHI ,  Tadamasa TOMA ,  Toru MATSUNOBU ,  Satoshi YOSHIKAWA ,  Tatsuya KOYAMA

IPC: G06T9/40 ,  G06T17/00 ,  G06T9/00 ,  G06T15/08

Abstract: A three-dimensional data encoding method includes: extracting, from first three-dimensional data, second three-dimensional data having an amount of a feature greater than or equal to a threshold; and encoding the second three-dimensional data to generate first encoded three-dimensional data. For example, the three-dimensional data encoding method may further include encoding the first three-dimensional data to generate the second encoded three-dimensional data.

公开(公告)号：US20210297692A1

公开(公告)日：2021-09-23

申请号：US17342076

申请日：2021-06-08

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Ryuichi KANOH ,  Takashi HASHIMOTO

IPC: H04N19/52 ,  H04N19/124 ,  H04N19/159 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry, in inter prediction processing: derives a first motion vector of a current block to be processed, using a motion vector of a previous block which has been previously processed; derives a second motion vector of the current block by performing motion estimation in the vicinity of the first motion vector; and generates a prediction image of the current block by performing motion compensation using the second motion vector.

公开(公告)号：US20210289205A1

公开(公告)日：2021-09-16

申请号：US17120995

申请日：2020-12-14

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Hideo SAITOU ,  Masato OHKAWA ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA ,  Yusuke KATO

IPC: H04N19/124 ,  H04N19/176 ,  H04N19/136 ,  H04N19/18 ,  H04N19/182

Abstract: An encoder includes circuitry and memory coupled to the circuitry. The circuitry, in operation: generates (i) a first quantization matrix for transform coefficients included in a current block to be processed and (ii) a second quantization matrix for transform coefficients included in a low frequency domain among the transform coefficients included in the current block; and quantizes the transform coefficients included in the current block using at least one of the first quantization matrix or the second quantization matrix, in accordance with a size of the current block.

公开(公告)号：US20210289198A1

公开(公告)日：2021-09-16

申请号：US17332132

申请日：2021-05-27

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ru Ling LIAO ,  Chong Soon LIM ,  Jing Ya LI ,  Han Boon TEO ,  Hai Wei SUN ,  Che Wei KUO ,  Yusuke KATO ,  Tadamasa TOMA ,  Kiyofumi ABE ,  Takahiro NISHI

IPC: H04N19/107 ,  H04N19/176

Abstract: An image encoder includes: circuitry; and a memory coupled to the circuitry. The circuitry, in operation: calculates first values of a current block using intra prediction, the intra prediction being limited to planar mode, the planar mode using multiple reference pixels for each pixel location of the current block; calculates second values of the current block using inter prediction; calculates third values of the current block by weighting the first values and the second values; and encodes the current block using the third values, and in the calculating of the third values, a first weight is applied to the first values and a second weight is applied to the second values, the second weight being different from the first weight.

公开(公告)号：US20210274172A1

公开(公告)日：2021-09-02

申请号：US17321834

申请日：2021-05-17

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Chong Soon LIM ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI ,  Che-Wei KUO ,  Kiyofumi ABE ,  Tadamasa TOMA ,  Takahiro NISHI ,  Yusuke KATO

IPC: H04N19/117 ,  H04N19/80 ,  H04N19/51 ,  H04N19/176

Abstract: An encoder that encodes a current block to be encoded in an image is provided. The encoder includes: processor; and memory coupled to the processor, in which, in operation, the processor: generates a first prediction image based on a motion vector, the first prediction image being an image with full-pel precision; generates a second prediction image using an interpolation filter by interpolating a value at a fractional-pel position between full-pel positions included in the first prediction image; and encodes the current block based on the second prediction image, and in the using of the interpolation filter, the interpolation filter is switched between a first interpolation filter and a second interpolation filter differing in a total number of taps from the first interpolation filter.

公开(公告)号：US20210258577A1

公开(公告)日：2021-08-19

申请号：US17306483

申请日：2021-05-03

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE ,  Ryuichi KANOH ,  Chong Soon LIM ,  Sughosh Pavan SHASHIDHAR ,  Ru Ling LIAO ,  Hai Wei SUN ,  Han Boon TEO ,  Jing Ya LI

IPC: H04N19/119 ,  H04N19/157 ,  H04N19/176

Abstract: An encoder partitions into blocks using a set of block partition modes. The set of block partition modes includes a first partition mode for partitioning a first block, and a second block partition mode for partitioning a second block which is one of blocks obtained after the first block is partitioned. When the number of partitions of the first block partition mode is three, the second block is a center block among the blocks obtained after partitioning the first block, and the partition direction of the second block partition mode is same as the partition direction of the first block partition mode, the second block partition mode indicates that the number of partitions is only three. A parameter for identifying the second block partition mode includes a first flag indicating a horizontal or vertical partition direction, and does not include a second flag indicating the number of partitions.

公开(公告)号：US20210227217A1

公开(公告)日：2021-07-22

申请号：US17227015

申请日：2021-04-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Ryuichi KANOH ,  Takahiro NISHI ,  Tadamasa TOMA ,  Kiyofumi ABE

IPC: H04N19/117 ,  H04N19/146 ,  H04N19/176

Abstract: A decoder comprises circuitry and memory. The circuitry, using the memory, in operation, determines a number of first pixels and a number of second pixels used in a deblocking filter process, wherein the first pixels are located at an upper side of a block boundary and the second pixels are located at a lower side of the block boundary, and performs the deblocking filter process on the block boundary. The number of the first pixels and the number of the second pixels are selected from among candidates, wherein the candidates include at least 4 and M larger than 4. Response to a location of the block boundary being a predetermined location, the number of the first pixels used in the deblocking filter process is limited to be 4.

公开(公告)号：US20210218970A1

公开(公告)日：2021-07-15

申请号：US17196194

申请日：2021-03-09

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Jing Ya LI ,  Ru Ling LIAO ,  Chong Soon LIM ,  Han Boon TEO ,  Hai Wei SUN ,  Kiyofumi ABE ,  Takahiro NISHI ,  Tadamasa TOMA

IPC: H04N19/159 ,  H04N19/182 ,  H04N19/117

Abstract: An encoder includes circuitry and memory connected to the circuitry. The circuitry: derives an absolute value of a sum of gradient values in first and second ranges; derives, as a first parameter, a total sum of absolute values of sums of gradient values derived respectively for pairs of relative pixel positions; derives a pixel difference value between pixel values in the first and second ranges; inverts or maintains a plus or minus sign of the pixel difference value, according to a plus or minus sign of the sum of the gradient values indicating the sum of the gradient values in the first and second ranges; derives, as a second parameter, a total sum of pixel difference values each having the plus or minus sign inverted or maintained, the pixel difference values derived respectively for the relative pixel positions; and generates a prediction image using the first and second parameters.

公开(公告)号：US20210099728A1

公开(公告)日：2021-04-01

申请号：US17117837

申请日：2020-12-10

Applicant: Panasonic Intellectual Property Corporation of America

Inventor： Tadamasa TOMA ,  Takahiro NISHI ,  Kiyofumi ABE

IPC: H04N19/51 ,  H04N19/176

Abstract: An encoder includes circuitry and memory. Using the memory, the circuitry: in an inter prediction mode in which an affine motion vector is calculated for each of sub-blocks constituting a current block of a picture in the video, based on motion vectors of neighboring blocks of the current block, changes a shape or size of the sub-block according to a variation in direction or variation in magnitude among the motion vectors of the neighboring blocks; calculates the affine motion vector for the sub-block having the shape or size changed; and performs the motion compensation for the sub-block having the shape or size changed.