公开(公告)号：US10199288B1

公开(公告)日：2019-02-05

申请号：US15942483

申请日：2018-03-31

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L21/66 ,  H01L27/02 ,  H01L23/528 ,  H01L23/58 ,  H01L29/06

Abstract: A method for processing a semiconductor wafer uses non-contact electrical measurements indicative of at least one side-to-side short or leakage, at least one corner short or leakage, and at least one via open or resistance, where such measurements are obtained from non-contact pads associated with respective side-to-side short, corner short, and via open test areas.

公开(公告)号：US10096378B1

公开(公告)日：2018-10-09

申请号：US15441002

申请日：2017-02-23

Applicant: PDF Solutions, Inc.

Inventor： Yih-Yuh Doong ,  Chao-Hsiung Lin ,  Sheng-Che Lin ,  Shihpin Kuo ,  Tzupin Shen ,  Chia-Chi Lin ,  Kimon Michaels

IPC: G11C29/00 ,  G11C29/02 ,  H03K17/687 ,  G11C8/08

Abstract: A capacitance measurement test vehicle comprises multiple product layers which are used to build memories except interconnect layers, and one or more customized interconnect layers to connect memory-bit-line-under-tests (MBLUTs), memory-world-line-under-tests (MWLUTs) and memory-bit-cell-under-tests (MUTs). By introducing two transistors, one PMOS and one NMOS, at two opposite sides or the same side of a bit-line or a world-line, the capacitance of the bit-line or the world-line can be measured by a parametric tester. The PMOS device is for pumping in current, and the NMOS device is for draining out the current. By applying a non-overlapping clocked signal at the PMOS and NMOS transistors, the capacitance of bit-line, word-line and bit-cell can be measured as current signal. The PMOS and NMOS transistors are selected from on-chip transistors that are already in the memory design layout.

公开(公告)号：US09929136B1

公开(公告)日：2018-03-27

申请号：US15475285

申请日：2017-03-31

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L27/00 ,  H01L27/02 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66 ,  H01L21/8234 ,  H01L27/088 ,  G06F11/07 ,  G06F17/50

CPC classification number: H01L22/20 ,  G01R31/303 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/823437 ,  H01L21/823475 ,  H01L22/26 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11803 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11888

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOES), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-side shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

公开(公告)号：US09922890B1

公开(公告)日：2018-03-20

申请号：US15721792

申请日：2017-09-30

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L21/66 ,  H01L27/118 ,  H01L29/417 ,  H01L27/02 ,  H01L23/528 ,  G06F11/07 ,  G06F17/50 ,  H01L29/06

CPC classification number: H01L22/20 ,  G01R31/303 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/823437 ,  H01L21/823475 ,  H01L22/26 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11803 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11888

Abstract: An integrated circuit, in the form of a wafer, die, or chip, includes multiple standard cell-compatible fill cells, configured to enable non-contact electrical measurements. Such fill cells include mesh pads that contain at least three conductive stripes disposed between adjacent gate stripes. Such fill cells further include geometry to enable non-contact evaluation of snake opens and/or resistances.

公开(公告)号：US09871028B1

公开(公告)日：2018-01-16

申请号：US15475242

申请日：2017-03-31

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L29/00 ,  H01L27/02 ,  H01L29/45 ,  H01L23/522 ,  H01L23/528 ,  H01L21/66 ,  H01L21/8234 ,  H01L27/088 ,  G06F17/50 ,  G06F11/07

CPC classification number: H01L22/20 ,  G01R31/303 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/823437 ,  H01L21/823475 ,  H01L22/26 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11803 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11888

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of tip-to-tip shorts, and the second DOE contains fill cells configured to enable NC detection of chamfer shorts. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

公开(公告)号：US09870966B1

公开(公告)日：2018-01-16

申请号：US15281508

申请日：2016-09-30

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L29/00 ,  H01L21/66 ,  H01L27/02 ,  H01L29/06 ,  G06F17/50 ,  G06F11/07

CPC classification number: H01L22/26 ,  G01R31/2884 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11885 ,  H01L2027/11887

Abstract: Improved processes for manufacturing semiconductor wafers, chips, or dies utilize in-line data obtained from non-contact electrical measurements (“NCEM”) of fill cells that contain structures configured to target/expose a variety of open-circuit, short-circuit, leakage, and/or excessive resistance failure modes. Such processes include evaluating one or more Designs of Experiments (“DOEs”), each comprised of multiple NCEM-enabled fill cells, in at least two variants, targeted to the same failure mode. Such DOEs include multiple means/steps for enabling non-contact (NC) detection of AACNT-TS via opens.

公开(公告)号：US09865583B1

公开(公告)日：2018-01-09

申请号：US15635595

申请日：2017-06-28

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L21/66 ,  H01L27/02 ,  H01L29/417 ,  H01L29/06 ,  H01L23/528

CPC classification number: H01L27/0207 ,  H01L22/26 ,  H01L23/528 ,  H01L29/0649 ,  H01L29/41725

Abstract: A process for making and using a semiconductor wafer includes instantiating first and second designs of experiments (DOEs), each comprised of at least two fill cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The first DOE contains fill cells configured to enable non-contact (NC) detection of snake opens, and the second DOE contains fill cells configured to enable NC detection of stitch opens. The process may further include obtaining NC measurements from the first and/or second DOE(s) and using such measurements, at least in part, to selectively perform additional processing, metrology or inspection steps on the wafer, and/or on other wafer(s) currently being manufactured.

公开(公告)号：US09799575B2

公开(公告)日：2017-10-24

申请号：US15090256

申请日：2016-04-04

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L29/00 ,  H01L21/66 ,  G06F11/07 ,  G06F17/50 ,  H01L27/02 ,  H01L29/06

CPC classification number: H01L22/26 ,  G01R31/2884 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11885 ,  H01L2027/11887

Abstract: Wafers, chips, or dies that contain fill cells with structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). Such NCEM-enabled fill cells may target/expose a variety of open-circuit, short-circuit, leakage, or excessive resistance failure modes. Such wafers, chips, or dies may include Designs of Experiments (“DOEs”), comprised of multiple NCEM-enabled fill cells, in at least two variants, all targeted to the same failure mode(s).

公开(公告)号：US09793253B1

公开(公告)日：2017-10-17

申请号：US15372331

申请日：2016-12-07

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L29/00 ,  H01L27/02 ,  H01L21/66 ,  H01L29/417 ,  H01L29/06 ,  H01L23/528 ,  G06F11/07 ,  G06F17/50

CPC classification number: H01L22/26 ,  G01R31/2884 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L22/20 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11807 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11885 ,  H01L2027/11887

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one AACNT-short-related failure mode, one GATE-short-related failure mode, and one metal-short-related failure mode.

公开(公告)号：US09780083B1

公开(公告)日：2017-10-03

申请号：US15392755

申请日：2016-12-28

Applicant: PDF Solutions, Inc.

Inventor： Stephen Lam ,  Dennis Ciplickas ,  Tomasz Brozek ,  Jeremy Cheng ,  Simone Comensoli ,  Indranil De ,  Kelvin Doong ,  Hans Eisenmann ,  Timothy Fiscus ,  Jonathan Haigh ,  Christopher Hess ,  John Kibarian ,  Sherry Lee ,  Marci Liao ,  Sheng-Che Lin ,  Hideki Matsuhashi ,  Kimon Michaels ,  Conor O'Sullivan ,  Markus Rauscher ,  Vyacheslav Rovner ,  Andrzej Strojwas ,  Marcin Strojwas ,  Carl Taylor ,  Rakesh Vallishayee ,  Larg Weiland ,  Nobuharu Yokoyama

IPC: H01L29/00 ,  H01L27/02 ,  H01L21/66 ,  H01L29/06 ,  G06F17/50 ,  G06F11/07

CPC classification number: H01L22/20 ,  G01R31/303 ,  G06F11/079 ,  G06F17/5045 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  G06F2217/06 ,  H01L21/823437 ,  H01L21/823475 ,  H01L22/26 ,  H01L22/32 ,  H01L22/34 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11803 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/0649 ,  H01L29/0684 ,  H01L29/0847 ,  H01L29/41725 ,  H01L29/45 ,  H01L2027/11866 ,  H01L2027/11875 ,  H01L2027/11888

Abstract: An IC includes logic cells, selected from a standard cell library, and fill cells, configured for compatibility with the standard logic cells. The fill cells contain structures configured to obtain in-line data via non-contact electrical measurements (“NCEM”). The IC includes such NCEM-enabled fill cells configured to enable detection and/or measurement of a variety of open-circuit and short-circuit failure modes, including at least one via-open-related failure mode, one TS-short-related failure mode, one metal-short-related failure mode, and one AA-short-related failure mode.