公开(公告)号：US06188622B1

公开(公告)日：2001-02-13

申请号：US09483264

申请日：2000-01-13

申请人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C2900

CPC分类号： G11C29/026 ,  G11C11/401 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6128240A

公开(公告)日：2000-10-03

申请号：US225811

申请日：1999-01-05

申请人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

发明人： Douglas J. Cutter ,  Fan Ho ,  Kurt D. Beigel

IPC分类号： G11C7/00 ,  G11C29/00

CPC分类号： G11C29/838

摘要： The cancellation of a redundant element of an integrated circuit with a cancel bank is disclosed. In one embodiment, a fuse or antifuse bank is coupled to the redundant element and permanently programmed to respond to the address of a defective primary element. If the redundant element is found to be defective, the fuse or antifuse bank is canceled, and a result the redundant element is also canceled. A cancel line of the fuse or antifuse bank, along with the cancel line of each of a plurality of other fuse or antifuse banks, is coupled to a cancel bank. The cancel bank comprises a multiplexer and a plurality of cancel antifuses less in number than the number of fuse or antifuse banks. The cancel antifuses are selectively enabled such that the fuse or antifuse bank coupled to the defective redundant element may be canceled.

公开(公告)号：US6052322A

公开(公告)日：2000-04-18

申请号：US363003

申请日：1999-07-28

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US6026040A

公开(公告)日：2000-02-15

申请号：US259220

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

发明人： Kurt D. Beigel ,  Douglas J. Cutter ,  Manny K. Ma ,  Gordon D. Roberts ,  James E. Miller ,  Daryl L. Habersetzer ,  Jeffrey D. Bruce ,  Eric T. Stubbs

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

摘要翻译： 作为存储器阵列的一部分，提供了用于改变施加到调节存储器阵列内的电通信的存取晶体管的驱动电路的电路。 在一个实施例中，该电路用于改变施加到感测放大器的电压 - 牵引晶体管的驱动，从而允许改变感测放大器部件的电压提升率。 将测试数据的样本写入存储器阵列，并以变化的驱动速率读取数次，以便确定感测放大器容纳外部电路的能力。 在另一个实施例中，电路用于改变施加到泄放装置的驱动，其调节存储器阵列的数字线与其单元板之间的通信。 减轻所述通信允许存储器阵列中的缺陷具有更显着的效果，并因此增加在测试期间发现这些缺陷的机会。 电路被配置为通过接触焊盘或耦合到电路的一系列离散电压源来接受和施加多个电压。

公开(公告)号：US5982686A

公开(公告)日：1999-11-09

申请号：US259219

申请日：1999-03-01

申请人： Kurt D. Beigel ,  Douglas J. Cutter

发明人： Kurt D. Beigel ,  Douglas J. Cutter

IPC分类号： G11C7/00 ,  G11C29/02 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/56

CPC分类号： G11C29/026 ,  G11C29/02 ,  G11C29/025 ,  G11C29/028 ,  G11C29/12 ,  G11C29/44 ,  G11C29/48 ,  G11C29/50 ,  G11C29/50012 ,  G11C29/56 ,  G11C11/401 ,  G11C2029/5004

摘要： As part of a memory array, a circuit is provided for altering the drive applied to an access transistor that regulates electrical communication within the memory array. In one embodiment, the circuit is used to alter the drive applied to a sense amp's voltage-pulling transistor, thereby allowing modification of the voltage-pulling rate for components of the sense amp. A sample of test data is written to the memory array and read several times at varying drive rates in order to determine the sense amp's ability to accommodate external circuitry. In another embodiment, the circuit is used to alter the drive applied to a bleeder device that regulates communication between the digit lines of the memory array and its cell plate. Slowing said communication allows defects within the memory array to have a more pronounced effect and hence increases the chances of finding such defects during testing. The circuit is configured to accept and apply a plurality of voltages, either through a contact pad or from a series of discrete voltage sources coupled to the circuit.

公开(公告)号：US5847987A

公开(公告)日：1998-12-08

申请号：US896701

申请日：1997-07-18

申请人： Douglas J. Cutter ,  Kurt D. Beigel ,  Fan Ho

发明人： Douglas J. Cutter ,  Kurt D. Beigel ,  Fan Ho

IPC分类号： G11C17/18 ,  G11C29/00 ,  G11C13/00

CPC分类号： G11C29/785 ,  G11C17/18 ,  G11C29/83

摘要： A programmable circuit includes a first node and provides a programmed signal based on the state of the first node. A first anti-fuse has a programmed state and an unprogrammed state and couples the first node to a first power supply when in the programmed state and decouples the first node from the first power supply when in the unprogrammed state. A second anti-fuse has a programmed state and an unprogrammed state and couples the first node to a second power supply when in the programmed state and decouples the first node from the second power supply when in the unprogrammed state. The state of the programmed signal can be used to replace a primary circuit element of an integrated circuit with a redundant circuit element.

公开(公告)号：US5706238A

公开(公告)日：1998-01-06

申请号：US783623

申请日：1997-01-14

申请人： Douglas J. Cutter ,  Kurt D. Beigel ,  Adrian E. Ong ,  Fan Ho ,  Patrick J. Mullarkey ,  Dien S. Luong ,  Brett Debenham ,  Kim M. Pierce

发明人： Douglas J. Cutter ,  Kurt D. Beigel ,  Adrian E. Ong ,  Fan Ho ,  Patrick J. Mullarkey ,  Dien S. Luong ,  Brett Debenham ,  Kim M. Pierce

IPC分类号： G11C17/18 ,  G11C17/16

CPC分类号： G11C17/18

摘要： An antifuse bank includes a bank of self-decoupling anti fuse circuits. The anti fuse circuits are programmed according to a pattern of address bits by blowing antifuses corresponding to bits of the address. The antifuses are blown by applying a high voltage across the antifuse. As each antifuse is blown, its resistance drops and current through the antifuse increases. The self-decoupling circuit detects the increased current flow and, when the anti fuse resistance is sufficiently low, limits current flow through the anti fuse. The antifuse thus does not load the high voltage source as other antifuses are blown.

摘要翻译： 反熔丝库包括一组自去耦反熔丝电路。 反熔丝电路根据地址位的模式通过吹出与地址的位相对应的反熔丝来编程。 通过在反熔丝上施加高电压来吹制反熔丝。 当每个反熔丝熔断时，其电阻下降，并且通过反熔丝的电流增加。 自解耦电路检测到增加的电流，当反熔丝电阻足够低时，限制电流通过反熔丝。 因此，反熔丝因其他反熔丝被吹制而不加载高压源。

公开(公告)号：US08319280B2

公开(公告)日：2012-11-27

申请号：US13231554

申请日：2011-09-13

申请人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

发明人： Kurt D. Beigel ,  Jigish D. Trivedi ,  Kevin G. Duesman

IPC分类号： H01L29/66

CPC分类号： H01L29/66621 ,  H01L27/10876

摘要： Semiconductor memory devices having recessed access devices are disclosed. In some embodiments, a method of forming the recessed access device includes forming a device recess in a substrate material that extends to a first depth in the substrate that includes a gate oxide layer in the recess. The device recess may be extended to a second depth that is greater that the first depth to form an extended portion of the device recess. A field oxide layer may be provided within an interior of the device recess that extends inwardly into the interior of the device recess and into the substrate. Active regions may be formed in the substrate that abut the field oxide layer, and a gate material may be deposited into the device recess.

摘要翻译： 公开了具有凹陷接入装置的半导体存储器件。 在一些实施例中，形成凹陷进入装置的方法包括在衬底材料中形成器件凹部，该衬底材料延伸到衬底中的第一深度，该第一深度包括凹陷中的栅极氧化物层。 装置凹部可以延伸到大于第一深度的第二深度，以形成装置凹部的延伸部分。 场氧化物层可以设置在器件凹部的内部，其内部延伸到器件凹部的内部并进入衬底。 活性区域可以形成在衬底中，其邻接场氧化物层，并且栅极材料可以沉积到器件凹部中。

公开(公告)号：US08273619B2

公开(公告)日：2012-09-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/8238

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。

公开(公告)号：US20100297822A1

公开(公告)日：2010-11-25

申请号：US12848662

申请日：2010-08-02

申请人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

发明人： Hongmei Wang ,  Kurt D. Beigel ,  Fred D. Fishburn ,  Rongsheng Yang

IPC分类号： H01L21/336 ,  H01L21/265

CPC分类号： H01L21/26513 ,  H01L21/324 ,  H01L21/823412 ,  H01L27/0811 ,  H01L27/088 ,  H01L29/66537 ,  H01L29/7833

摘要： The invention includes methods of forming channel region implants for two transistor devices simultaneously, in which a mask is utilized to block a larger percentage of a channel region location of one of the devices relative to the other. The invention also pertains to methods of forming capacitor structures in which a first capacitor electrode is spaced from a semiconductor substrate by a dielectric material, a second capacitor electrode comprises a conductively-doped diffusion region within the semiconductor material, and a capacitor channel region location is beneath the dielectric material and adjacent the conductively-doped diffusion region. An implant mask is formed to cover only a first portion of the capacitor channel region location and to leave a second portion of the capacitor channel region location uncovered. While the implant mask is in place, dopant is implanted into the uncovered second portion of the capacitor channel region location.

摘要翻译： 本发明包括同时形成两个晶体管器件的沟道区域植入物的方法，其中掩模用于阻挡相对于另一个器件之一的较大百分比的沟道区域位置。 本发明还涉及形成电容器结构的方法，其中第一电容器电极通过电介质材料与半导体衬底隔开，第二电容器电极包括半导体材料内的导电掺杂扩散区，电容器通道区位置为 在介电材料的下方并与导电掺杂的扩散区相邻。 形成注入掩模以仅覆盖电容器沟道区位置的第一部分并且留下未覆盖的电容器沟道区位置的第二部分。 当植入掩模就位时，掺杂剂被注入到电容器通道区域位置的未覆盖的第二部分中。