公开(公告)号：US07795953B2

公开(公告)日：2010-09-14

申请号：US12051465

申请日：2008-03-19

申请人： Ryu Ogiwara ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G05F1/10

CPC分类号： G11C5/147

摘要： According to an aspect of the present invention, there is provided a voltage step-down circuit including: a first NMOS connected between an external and an internal power-supply voltages through a PMOS turned ON during an active state and turned OFF during a standby state; a second NMOS connected between the external and the internal power-supply voltages; and a current control circuit that sinks a current from the internal power-supply voltage to a ground level for a certain period of time after an operation state is switched from the active state to the standby state.

摘要翻译： 根据本发明的一个方面，提供了一种电压降压电路，包括：第一NMOS，其连接在通过在激活状态期间导通的PMOS的外部和内部电源电压之间，并且在待机状态期间断开 ; 连接在外部和内部电源电压之间的第二NMOS; 以及电流控制电路，其在将动作状态从活动状态切换到待机状态之后，将电流从内部电源电压吸收到地电平一段时间。

公开(公告)号：US07763991B2

公开(公告)日：2010-07-27

申请号：US12266143

申请日：2008-11-06

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H02J1/10

CPC分类号： G05F1/575 ,  G05F3/16 ,  Y10T307/50

摘要： A voltage generating circuit comprising: a switching device which includes a first end connected to a high potential side power source, and which becomes conductive in a first mode and becomes non-conductive in a second mode; a first transistor including a first main electrode connected to a second end of the switching device, a second main electrode connected to an output terminal, and a gate connected to a gate potential supply node; a second transistor including a first main electrode connected to the high potential side power source, a second main electrode connected to the output terminal, and a gate connected to the gate potential supply node; and a gate voltage stabilizing circuit that suppresses a fluctuation in potential of the potential supply node, the fluctuation accompanying a change between the first and second modes.

摘要翻译： 一种电压产生电路，包括：开关装置，其包括连接到高电位侧电源的第一端，并且在第一模式中变为导通并且在第二模式中变为不导通; 第一晶体管，包括连接到开关装置的第二端的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 第二晶体管，包括连接到高电位侧电源的第一主电极，连接到输出端子的第二主电极和连接到栅极电位供应节点的栅极; 以及抑制电源供给节点的电位波动的栅极电压稳定电路，伴随着第一和第二模式之间的变化的波动。

公开(公告)号：US07759928B2

公开(公告)日：2010-07-20

申请号：US11937056

申请日：2007-11-08

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G01R31/02

CPC分类号： G01R31/3004 ,  G11C29/12005 ,  G11C29/50

摘要： According to an aspect of the invention, there is provided, a semiconductor device, including an internal voltage generation circuit generating a prescribed voltage, a first test circuit connecting to a voltage-supplying wiring, one end of the voltage-supplying wiring being connected to a source wiring and the other end of the voltage-supplying wiring being connected to the internal voltage generation circuit, the first test circuit being supplied an outer voltage from the source wiring and a voltage of the internal voltage generation circuit through the voltage-supplying wiring, the first test circuit generating a prescribed resistance value on a basis of a control input from an outer portion in a test mode.

摘要翻译： 根据本发明的一个方面，提供了一种半导体器件，包括产生规定电压的内部电压产生电路，连接到电压供给布线的第一测试电路，所述电压供给布线的一端连接到 源极布线和电压供给布线的另一端连接到内部电压产生电路，第一测试电路通过电压布线从源极布线提供外部电压和内部电压产生电路的电压 ，所述第一测试电路基于来自测试模式中的外部的控制输入而产生规定的电阻值。

公开(公告)号：US07750723B2

公开(公告)日：2010-07-06

申请号：US11959962

申请日：2007-12-19

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G05F3/20

CPC分类号： G11C11/4074 ,  G11C5/147

摘要： According to an aspect of the present invention, there is provided a voltage generation circuit including: first and second reference terminals to output first and second reference voltages, respectively; first PMOS and first NMOS transistors connected between high and low level power supply lines in series; an output terminal connected between the first PMOS and first NMOS transistors; a first operational amplifier including: first input terminals each including a gate of a PMOS transistor to be connected to one of the second reference terminal and the output terminal, and a first output terminal connected to the first PMOS transistor; and a second operational amplifier including: second input terminals each including a gate of an NMOS transistor to be connected to one of the first reference terminal and the output terminal, and a second output terminal connected to the first NMOS transistor.

摘要翻译： 根据本发明的一个方面，提供了一种电压产生电路，包括：分别输出第一和第二参考电压的第一和第二参考端子; 第一PMOS和第一NMOS晶体管串联在高低电平电源线之间; 连接在第一PMOS和第一NMOS晶体管之间的输出端子; 第一运算放大器，包括：第一输入端子，每个包括要连接到第二参考端子和输出端子之一的PMOS晶体管的栅极;以及连接到第一PMOS晶体管的第一输出端子; 以及第二运算放大器，包括：第二输入端子，每个包括要连接到第一参考端子和输出端子之一的NMOS晶体管的栅极，以及连接到第一NMOS晶体管的第二输出端子。

公开(公告)号：US20100091547A1

公开(公告)日：2010-04-15

申请号：US12553819

申请日：2009-09-03

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C7/00 ,  G11C5/14 ,  G11C7/06

CPC分类号： G11C11/22

摘要： A memory includes a memory cell array including destructive read-out type memory cells; a decoder selecting a cell; a sense amplifier configured to detect the data; and a read and write controller controlling a read operation and a write operation, wherein the read and write controller outputs a logical value of a write enable signal at the start of the read operation in a first period and makes the write enable signal invalid after the read operation starts during the first period, on the basis of the write enable signal and a restore signal keeping an activated state during the first period, the write enable signal being a signal allowing the write operation, the first period being a period from when the read operation starts to when a restore operation for writing the data back to the memory cell is completed.

摘要翻译： 存储器包括包括破坏性读出型存储单元的存储单元阵列; 选择单元的解码器; 感测放大器，被配置为检测所述数据; 以及控制读取操作和写入操作的读取和写入控制器，其中所述读取和写入控制器在第一周期中在所述读取操作开始时输出写入使能信号的逻辑值，并使所述写入使能信号在所述写入使能信号之后无效 在第一时段期间，基于写使能信号和恢复信号在第一时段期间保持激活状态的读操作开始，写使能信号是允许写操作的信号，第一周期是从 当将数据写入存储单元的恢复操作完成时，读操作开始。

公开(公告)号：US20070274132A1

公开(公告)日：2007-11-29

申请号：US11671107

申请日：2007-02-05

申请人： Ryu Ogiwara ,  Shinichiro Shiratake ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Shinichiro Shiratake ,  Daisaburo Takashima

IPC分类号： G11C11/22 ,  G11C11/34

CPC分类号： G11C5/14

摘要： A discharge order control circuit includes a pool circuit, a delay circuit and a discharge unit to control a discharge order of internal power supplies. The pool circuit stores electric charges provided from a potential of an external power supply. The delay circuit operates on the electric charges stored in the pool circuit and delays a discharge signal generated when potential of the external power supply is lowered to a predetermined potential level. The delay circuit includes an inverter array having a plurality of stages each containing an inverter. The plurality of stages include a final stage that outputs the delayed discharge signal. Only the inverter of the final stage generates an RC delay. The discharge unit discharges a internal power supply included in the internal power supplies in response to the delayed discharge signal output from the inverter of the final stage of the inverter array.

摘要翻译： 放电顺序控制电路包括用于控制内部电源的放电顺序的池电路，延迟电路和放电单元。 池电路存储从外部电源的电位提供的电荷。 延迟电路对存储在池电路中的电荷进行操作，并且当外部电源的电位降低到预定电位电平时，延迟产生的放电信号。 延迟电路包括具有多个级的逆变器阵列，每个级包含反相器。 多个级包括输出延迟放电信号的最后级。 只有最终级的逆变器产生RC延迟。 放电单元响应于从逆变器阵列的最后级的逆变器输出的延迟的放电信号，对包括在内部电源中的内部电源进行放电。

公开(公告)号：US20070236260A1

公开(公告)日：2007-10-11

申请号：US11684214

申请日：2007-03-09

申请人： Ryu Ogiwara ,  Daisaburo Takashima

发明人： Ryu Ogiwara ,  Daisaburo Takashima

IPC分类号： H03K5/22 ,  H03L7/00

CPC分类号： G01R19/16552 ,  G01R19/16519 ,  G11C5/147

摘要： A supply voltage sensing circuit comprises an internal power supply circuit, which provides a constant output voltage regardless of the supply voltage. A delay circuit generates a delayed signal by delaying a variation in the output voltage. A divider circuit generates a divided voltage by dividing the supply voltage at a certain division ratio. A p-type MOS transistor has a source given the delayed signal and a gate given the divided voltage and turns on when the supply voltage lowers below a certain value. An output circuit provides an output voltage based on a drain voltage on the p-type MOS transistor.

摘要翻译： 电源电压检测电路包括内部电源电路，其提供恒定的输出电压，而不管电源电压如何。 延迟电路通过延迟输出电压的变化来产生延迟信号。 分压电路通过以一定的分频比除电源电压来产生分压。 p型MOS晶体管具有给定延迟信号的源极和给定分压的栅极，并且当电源电压降低到一定值以下时导通。 输出电路基于p型MOS晶体管的漏极电压提供输出电压。

公开(公告)号：US07092304B2

公开(公告)日：2006-08-15

申请号：US10931978

申请日：2004-09-02

申请人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

发明人： Ryu Ogiwara ,  Daisaburo Takashima ,  Thomas Roehr

IPC分类号： G11C7/04

CPC分类号： G11C7/14 ,  G03B42/02 ,  G11C7/04 ,  G11C11/22

摘要： A dummy capacitor drive potential VDC is given to one electrode of a dummy capacitor, and a reference potential for determining a data value of a memory cell is generated in the other electrode thereof. A potential generator circuit for generating the potential VDC is composed of a BGR circuit outputting a potential VBGRTEMP having temperature dependency, and resistors R3 and R4, which are series-connected between an output terminal of the BGR circuit and a ground point. The potential VDC is output from a connection point of the resistors R3 and R4. Temperature dependency of the potential VDC is adjusted based on a resistance ratio of resistors R1-1, R1-2 and R2, and the absolute value is adjusted based on a resistance ratio of resistors R3 and R4.

摘要翻译： 虚拟电容器驱动电位VDC被提供给虚拟电容器的一个电极，并且在其另一个电极中产生用于确定存储器单元的数据值的参考电位。 用于产生电位VDC的潜在发电机电路由输出具有温度依赖性的电位VBGRTEMP的BGR电路和串联连接在BGR电路的输出端子与接地点之间的电阻器R 3和R 4构成。 从电阻器R 3和R 4的连接点输出电位VDC。 电阻VDC的温度依赖性根据电阻器R 1 - 1，R 1 - 2和R 2的电阻比进行调整，并且绝对值根据电阻器R 3和R 4的电阻比进行调整。

公开(公告)号：US06944046B2

公开(公告)日：2005-09-13

申请号：US10716565

申请日：2003-11-20

申请人： Ryu Ogiwara

发明人： Ryu Ogiwara

IPC分类号： G01R31/28 ,  G11C11/22 ,  G11C11/24 ,  G11C29/00 ,  G11C29/08 ,  G11C29/50 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C29/08 ,  G11C11/22

摘要： A ferroelectric memory comprising a plurality of memory cells each including a ferroelectric capacitor and a switch transistor, and operating in a test mode in which, after polarized data is written into the memory cell by applying a first electric potential difference between both electrodes of ferroelectric capacitors of the plurality of memory cells, and before reading of the polarized data from the memory cells is carried out, a second electric potential difference smaller than the first electric potential difference is applied between both the electrodes of the ferroelectric capacitors in a direction opposite to that at the time of writing the polarized data.

摘要翻译： 一种强电介质存储器，包括多个存储单元，每个存储单元包括铁电电容器和开关晶体管，并且在经过强电介质电容器的两个电极之间施加第一电位差而将偏振数据写入存储单元之后的测试模式下工作 并且在从存储单元读取偏振数据之前，在强电介质电容器的两个电极之间沿相反方向施加小于第一电位差的第二电位差 在写入极化数据时。

公开(公告)号：US06980460B2

公开(公告)日：2005-12-27

申请号：US10803935

申请日：2004-03-19

申请人： Shinichiro Shiratake ,  Ryu Ogiwara

发明人： Shinichiro Shiratake ,  Ryu Ogiwara

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： A semiconductor integrated circuit device includes first and second bit lines (BLs), first and second plate lines (PLs), a first series connected TC unit type structure connected between the first BL and the first PL, a second series connected TC unit type structure connected between the second BL and the second PL, a PL potential control circuit, and a BL potential control circuit. The PL potential control circuit controls a potential of the first PL from a first potential to a second potential and a potential of the second PL from the first potential to a third potential, when the first series connected TC unit type structure is selected. The BL potential control circuit controls a potential of the second BL to the third potential, after charges are transferred from the first series connected TC unit type structure to the first BL.