公开(公告)号：US11574693B2

公开(公告)日：2023-02-07

申请号：US17347772

申请日：2021-06-15

Applicant: SanDisk Technologies LLC

Inventor： Chin-Yi Chen ,  Muhammad Masuduzzaman ,  Dengtao Zhao ,  Anubhav Khandelwal ,  Ravi Kumar

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/08 ,  G11C16/28 ,  G11C16/16

Abstract: A memory apparatus and method of operation are provided. The apparatus includes memory cells connected to one of a plurality of word lines and arranged in strings and configured to retain a threshold voltage corresponding to one of a plurality of memory states. A control circuit is coupled to the plurality of word lines and strings and is configured to erase the memory cells using a stripe erase operation in response to determining a cycle count is less than a predetermined cycle count maximum threshold. The control circuit is also configured to perform a dummy cycle operation in response to determining the cycle count is not less than the predetermined cycle count maximum threshold.

公开(公告)号：US11201111B2

公开(公告)日：2021-12-14

申请号：US16697560

申请日：2019-11-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Zhiping Zhang ,  Peng Zhang ,  Deepanshu Dutta

IPC: H01L27/11578 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06 ,  G11C16/16 ,  H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11519

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, where the electrically conductive layers comprise word lines located between a source select gate electrode and a drain select gate electrode, a memory opening vertically extending through each layer of the alternating stack to a top surface of the substrate, a memory film and vertical semiconductor channel having a doping of a first conductivity type located in the memory opening, and an active region having a doping of a second conductivity type that is an opposite of the first conductivity type and adjoined to an end portion of the vertical semiconductor channel to provide a p-n junction. The end portion of the vertical semiconductor channel has a first thickness, and a middle portion of the vertical semiconductor channel has a second thickness which is less than the first thickness.

公开(公告)号：US11062780B1

公开(公告)日：2021-07-13

申请号：US16729951

申请日：2019-12-30

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Huai-Yuan Tseng ,  Jiahui Yuan ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: Method(s) and structure(s) for a two-page read operation are described and provide a multiple page read. The two page read operation provides for reading two pages with in a block without reducing the control gates to a low voltage level. The two page read can read the first page using an incrementing voltage level at discrete steps and starting the second page read at the high state for the control gates from the first page read. The second page read then decrements the control gate voltages level through the steps. This should reduce energy consumption. The two-page read operation will also reduce the time as the time period to reset the control gates to a low state are not required in between the page read operations.

公开(公告)号：US20210134372A1

公开(公告)日：2021-05-06

申请号：US16676023

申请日：2019-11-06

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Peng Zhang ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/34 ,  G06F3/06

Abstract: A method reading memory using bi-directional sensing, including programming first memory cells coupled to a first word-line using a normal programming order; programming second memory cells coupled to a second word-line using a normal programming order; reading data from the first memory cells by applying a normal sensing operation to the first word-line; and reading data from the second memory cells by applying a reverse sensing operation to the second word-line. Methods also include receiving an error associated with reading data from the first memory cells; and then reading the data from the first memory cells by applying a reverse sensing operation to the first word-line. Method also include receiving an error associated with reading the data from the second memory cells; and then reading the data from the second memory cells by applying a normal sensing operation to the second word-line.

公开(公告)号：US20210134370A1

公开(公告)日：2021-05-06

申请号：US16701450

申请日：2019-12-03

Applicant: SanDisk Technologies LLC

Inventor： Zhiping Zhang ,  Muhammad Masuduzzaman ,  Huai-Yuan Tseng ,  Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/12 ,  G11C16/10 ,  G11C16/24 ,  G11C16/34 ,  G11C16/26

Abstract: A method of concurrently programming a memory. Various methods include: applying a non-negative voltage on a first bit line coupled to a first memory cell; applying a negative voltage on a second bit line coupled to a second memory cell, where the negative voltage is generated using triple-well technology; then applying a programming pulse to the first and second memory cells concurrently; and in response, programming the first and second memory cells to different states. The methods also include applying a quick pass write operation to the first and second memory cells, by: applying a quick pass write voltage to the first bit line coupled to the first memory cell, where the quick pass write voltage is higher than the non-negative voltage; applying a negative quick pass write voltage to the second bit line coupled to the first memory cell, where the negative quick pass write voltage is generated using triple-well technology.

公开(公告)号：US10553298B1

公开(公告)日：2020-02-04

申请号：US16047599

申请日：2018-07-27

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/10 ,  G11C16/34 ,  H01L27/11582 ,  G11C16/04 ,  G11C16/08

Abstract: Program disturb is a condition that includes the unintended programming while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a dummy word line to another side of the dummy word line and redirected into a select gate. To prevent such program disturb, it is proposed to open the channel from one side of the dummy word line to the other side of the dummy word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied. For example, the channel can be opened up by applying a voltage to the dummy word line prior to pre-charging unselected memory cells.

公开(公告)号：US20190378579A1

公开(公告)日：2019-12-12

申请号：US16002793

申请日：2018-06-07

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Dengtao Zhao ,  Deepanshu Dutta

IPC: G11C16/34 ,  G11C16/12 ,  G11C16/04 ,  G11C7/04 ,  G11C8/08

Abstract: Program disturb is a condition that includes the unintended programming of a memory cell while performing a programming process for other memory cells. Such unintended programming can cause an error in the data being stored. In some cases, program disturb can result from electrons trapped in the channel being accelerated from one side of a selected word line to another side of the selected word line and redirected into the selected word line. To prevent such program disturb, it is proposed to open the channel from one side of a selected word line to the other side of the selected word line after a sensing operation for program verify and prior to a subsequent programming voltage being applied.