中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

64 records (took 0.021 seconds)

    Electromagnetic bandgap structure and printed circuit board
    51.
    发明授权
    Electromagnetic bandgap structure and printed circuit board 有权
    电磁带隙结构和印刷电路板

    公开(公告)号：US08710943B2

    公开(公告)日：2014-04-29

    申请号：US13756210

    申请日：2013-01-31

    Applicant: Samsung Electro-Mechanics Co., Ltd.

    Inventor： Han Kim ,  Hyung-Sik Choi ,  Sang-Hoon Kim ,  Joon-Sung Kim

    IPC: H01P1/203

    CPC classification number: H05K1/116 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0236 ,  H05K2201/09309 ,  H05K2201/09627 ,  H01L2224/0401

    Abstract: An electromagnetic bandgap structure and a printed circuit board that can solve a mixed signal problem between an analog circuit and a digital circuit are disclosed. In accordance with an embodiment, an electromagnetic bandgap structure is stacked with a first metal layer, a first dielectric layer, a metal plate, a second dielectric layer and a second metal layer, and an odd number of vias can be serially connected through a metal line between the first metal layer and the metal plate. This electromagnetic bandgap structure can have a small size and a low bandgap frequency.

    Abstract translation: 公开了可解决模拟电路和数字电路之间的混合信号问题的电磁带隙结构和印刷电路板。 根据实施例，电磁带隙结构与第一金属层，第一介电层，金属板，第二介电层和第二金属层堆叠，并且奇数通孔可以通过金属串联连接 第一金属层和金属板之间的线。 该电磁带隙结构可以具有小尺寸和低带隙频率。

    CAPACITOR-EMBEDDED PRINTED CIRCUIT BOARD
    52.
    发明申请
    CAPACITOR-EMBEDDED PRINTED CIRCUIT BOARD 审中-公开
    电容式嵌入式印刷电路板

    公开(公告)号：US20140003012A1

    公开(公告)日：2014-01-02

    申请号：US13800760

    申请日：2013-03-13

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Doo Hwan LEE ,  Jong In Ryu ,  Dae Hyun Park ,  Han Kim

    IPC: H05K1/18

    CPC classification number: H05K1/182 ,  H05K1/0231 ,  H05K1/185

    Abstract: Disclosed herein is a capacitor-embedded printed circuit board, including first to fourth layers forming a four-layer laminated structure; and one or more capacitors embedded through the second layer and the third layer among the first to fourth layers, wherein the respective capacitors embedded through the second layer and the third layer are electrically connected to one or more power terminals of active elements and ground terminals, and wherein at the second or third layer, power terminal wirings are connected to thereby allow the capacitors to form a mutual parallel connection structure, and thus, in embedding capacitors in a laminated structured board having a plurality of layers, a capacitor-embedded printed circuit board capable of reducing the impedance in the entire frequency region and having a high capacitance and a low equivalent series inductance can be realized by effectively connecting capacitors embedded inside the printed circuit board in parallel with each other.

    Abstract translation: 这里公开了一种电容器嵌入式印刷电路板，包括形成四层层叠结构的第一至第四层; 以及通过第一至第四层中的第二层和第三层嵌入的一个或多个电容器，其中通过第二层和第三层嵌入的各个电容器电连接到有源元件和接地端子的一个或多个电源端子， 并且其中在第二或第三层连接有电源端子布线，从而允许电容器形成相互平行的连接结构，因此在将电容器嵌入具有多个层的叠层结构板中时，电容器嵌入的印刷电路 可以通过有效地将嵌入在印刷电路板内的电容器彼此并联来实现，从而可以实现整个频率区域中的阻抗并具有高电容和低等效串联电感的板。

    Multi-layered ceramic electronic component and mounting board thereof
    55.
    发明授权
    Multi-layered ceramic electronic component and mounting board thereof 有权

    公开(公告)号：US11081283B2

    公开(公告)日：2021-08-03

    申请号：US16561457

    申请日：2019-09-05

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Yun Tae Lee ,  Kyung Moon Jung ,  Han Kim

    IPC: H01G4/30 ,  H01G4/012 ,  H01G2/06 ,  H01G4/228 ,  H01G4/12

    Abstract: A multilayer ceramic electronic component and a mounting board thereof include a reinforcing member that is disposed on upper and lower surfaces of a ceramic body of the multilayer ceramic electronic component and that is bonded to the first and the second external electrodes. The reinforcing member provides reduced occurrence of cracking and reduced stress applied to the component. The reinforcing member may have a coefficient of thermal expansion (CTE) that is within a range of 1 to 4 times a coefficient of thermal expansion of a dielectric layer of the ceramic body, and/or may have a modulus that is 0.5 or more times a modulus of the dielectric layer.

    Semiconductor package
    56.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US10943878B2

    公开(公告)日：2021-03-09

    申请号：US16586529

    申请日：2019-09-27

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Yun Tae Lee ,  Han Kim ,  Hyung Joon Kim

    IPC: H01L23/48 ,  H01L23/00 ,  H01L23/495

    Abstract: A semiconductor package includes a frame having a recess on which a stopper layer is disposed, a semiconductor chip including a body having a first surface on which a connection pad is disposed and a second surface opposing the first surface, and a through-via penetrating through at least a portion of a region between the first surface and the second surface, the second surface facing the stopper layer, an encapsulant covering at least a portion of each of the frame and the semiconductor chip and filling at least a portion of the recess, a first connection structure disposed on a lower side of the frame and on the first surface of the semiconductor chip and including a first redistribution layer, and a second connection structure disposed on an upper side of the frame and on the second surface of the semiconductor chip and including a second redistribution layer.

    ANTENNA MODULE
    57.
    发明申请
    ANTENNA MODULE 审中-公开

    公开(公告)号：US20200020653A1

    公开(公告)日：2020-01-16

    申请号：US16284289

    申请日：2019-02-25

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Jae Hyun Lim ,  Han Kim ,  Chul Kyu Kim ,  Sang Jong Lee ,  Jung Ho Shim

    IPC: H01L23/66 ,  H01Q1/24 ,  H01L23/00

    Abstract: An antenna module includes an antenna substrate including a core layer, insulating layers disposed on opposite surfaces of the core layer, and wiring layers including antenna patterns. The antenna substrate has first and second recess portions. The antenna module further includes a passive component disposed in the first recess portion, a semiconductor chip disposed in the second recess portion and having an active surface, an encapsulant encapsulating at least portions of the semiconductor chip and the passive component, and a connection portion disposed on the active surface of the semiconductor chip and including redistribution layers electrically connected to the semiconductor chip. The passive component has a thickness greater than that of the semiconductor chip, and the first recess portion has a depth greater than that of the second recess portion.

    Fan-out semiconductor package
    60.
    发明授权
    Fan-out semiconductor package 有权

    公开(公告)号：US10304784B2

    公开(公告)日：2019-05-28

    申请号：US15938181

    申请日：2018-03-28

    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

    Inventor： Jong Man Kim ,  Han Kim ,  Kyung Ho Lee

    IPC: H01L23/00 ,  H01L23/31 ,  H01L23/495 ,  H01L25/065 ,  H01L21/48 ,  H01L23/538

    Abstract: A fan-out semiconductor package includes a wiring portion, semiconductor chips, a dummy chip, and an encapsulant. The wiring portion includes an insulating layer, conductive patterns formed on the insulating layer, and conductive vias penetrating through the insulating layer and connected to the conductive patterns. The semiconductor chips are disposed on one region of the wiring portion, and the dummy chip is disposed on another region thereof and has a thickness smaller than those of the semiconductor chips. The encapsulant encapsulates at least portions of the semiconductor chips and the dummy chip. An upper surface of the wiring portion is disposed below a center line of the fan-out semiconductor package, and the thickness t of the dummy chip is such that T/2≤t≤3T/2 in which T is a distance from the upper surface of the wiring portion to the center line of the fan-out semiconductor package.

Patent Agency Ranking