公开(公告)号：US06714456B1

公开(公告)日：2004-03-30

申请号：US10058461

申请日：2002-01-28

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0425 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L27/11524

摘要： An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

摘要翻译： 一种快速程序，超高密度，双位，多级闪存过程，可应用于弹道式分闸门侧壁晶体管，或可应用于弹道平面分裂栅侧壁晶体管，可实现程序运行 描述了程序中浮栅的低电压要求。 两个侧壁浮动栅极与单个字线选择栅极配对，并且字线被布置成垂直于位线和控制栅极线。 同一字线上的两个相邻的存储单元不需要隔离区。 此外，利用自对准填充技术，由最小光刻特征限定共享相同位线的相邻存储单元之间的隔离区域。 相同字线上的相邻存储单元共享位线扩散以及第三个多路控制门。 控制门允许对各个浮动门的程序和读取访问。 除了单元的双位特性之外，还可以通过多级存储进一步提高密度。 在一个实施例中，双重多层结构被应用于弹道分割栅侧壁晶体管。 在第二实施例中，双重多层结构被应用于弹道平面分裂栅侧壁晶体管。 两种类型的弹道晶体管都提供快速，低电压编程。 控制栅极用于覆盖或抑制相关浮动栅极上的各种阈值电压，以便编程到单个浮动栅极并从其读取。 该非易失性存储器阵列的目标是提供高速，低电压编程（带宽）和高密度存储的能力。

公开(公告)号：US06567314B1

公开(公告)日：2003-05-20

申请号：US10003842

申请日：2001-12-04

申请人： Tomoko Ogura ,  Seiki Ogura

发明人： Tomoko Ogura ,  Seiki Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C7/18 ,  G11C16/0466

摘要： In the present invention a new method and circuit is disclosed to handle write data during CHE programming for a nonvolatile memory cell including cells created with MONOS technology. A plurality of bit lines are precharged to program inhibit all memory cells coupled to the bit lines. Then a selective bit line is discharged to program the selected memory cell. The number of bit lines selected to be precharged can be reduced to the bit line to be programmed to save power, and precharging a bit line can be done simultaneous with applying program data to a bit line to reduce the number of times a bit line is charged. The number of data latches may be reduced to the actual program data width, resulting in significant area savings and circuit simplification.

摘要翻译： 在本发明中，公开了一种新的方法和电路，用于在包括使用MONOS技术创建的单元的非易失性存储单元的CHE编程期间处理写入数据。 多个位线被预充电以编程禁止耦合到位线的所有存储器单元。 然后，选择性位线被排出以对所选择的存储单元进行编程。 选择预充电的位线的数量可以减少到要编程的位线以节省功率，并且可以同时进行预充电，同时将程序数据应用于位线以减少位线的次数 带电。 数据锁存器的数量可以减少到实际的程序数据宽度，导致显着的面积节省和电路简化。

公开(公告)号：US06359807B1

公开(公告)日：2002-03-19

申请号：US09656394

申请日：2000-09-06

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458 ,  G11C16/0475 ,  G11C2211/5612 ,  H01L27/115 ,  H01L27/11524

摘要： An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

公开(公告)号：US6133098A

公开(公告)日：2000-10-17

申请号：US313302

申请日：1999-05-17

申请人： Seiki Ogura ,  Tomoko Ogura

发明人： Seiki Ogura ,  Tomoko Ogura

IPC分类号： G11C11/56 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/115

CPC分类号： H01L27/11521 ,  G11C11/5621 ,  G11C16/0458 ,  G11C16/0475 ,  H01L27/115 ,  H01L27/11524 ,  G11C2211/5612

摘要： An fast program, ultra-high density, dual-bit, multi-level flash memory process, which can be applied to a ballistic step split gate side wall transistor, or to a ballistic planar split gate side wall transistor, which enables program operation by low voltage requirement on the floating gate during program is described. Two side wall floating gates are paired with a single word line select gate, and word lines are arranged to be perpendicular both the bit lines and control gate lines. Two adjacent memory cells on the same word line do not require an isolation region. Also, the isolation region between adjacent memory cells sharing the same bitline is defined by the minimum lithography feature, utilizing a self align fill technique. Adjacent memory cells on the same word line share bitline diffusion as well as a third poly control gate. Control gates allow program and read access to the individual floating gate. In addition to the dual-bit nature of the cell, density can be even further improved by multi-level storage. In one embodiment, the dual multi-level structure is applied to the ballistic step split gate side wall transistor. In a second embodiment, the dual multi-level structure is applied to the ballistic planar split gate side wall transistor. Both types of ballistic transistors provide fast, low voltage programming. The control gates are used to override or suppress the various threshold voltages on associated floating gates, in order to program to and read from individual floating gates. The targets for this non-volatile memory array are to provide the capabilities of high speed, low voltage programming (band width) and high density storage.

公开(公告)号：US06631089B1

公开(公告)日：2003-10-07

申请号：US10190636

申请日：2002-07-08

申请人： Nori Ogura ,  Tomoko Ogura

发明人： Nori Ogura ,  Tomoko Ogura

IPC分类号： G11C1606

CPC分类号： G11C16/0475 ,  G11C16/08

摘要： In the present invention a bit line decoder circuit a method of selecting bit lines for read and program operations is described for a twin MONOS memory cell array. A block of twin MONOS memory cells is partitioned into sub-blocks wherein decode signals select bit lines to be read and programmed, and select adjacent bit lines to provide bias for the read and program operations. The bit lines are partitioned into even and odd addresses within each sub-block, and an even and odd address sub-block selector connects the selected bit line along with adjacent bit lines to sense amplifiers and memory chip I/O.

摘要翻译： 在本发明中，对于双MONOS存储单元阵列描述了位线解码器电路，用于选择用于读取和编程操作的位线的方法。 双MONOS存储器单元的块被分割成子块，其中解码信号选择要被读取和编程的位线，并且选择相邻位线以提供读取和编程操作的偏置。 位线被划分成每个子块内的偶数和奇数地址，偶数和奇数地址子块选择器将所选位线与相邻位线连接到读出放大器和存储器芯片I / O。

公开(公告)号：US06643172B2

公开(公告)日：2003-11-04

申请号：US10190633

申请日：2002-07-08

申请人： Tomoko Ogura

发明人： Tomoko Ogura

IPC分类号： G11C1604

CPC分类号： G11C16/24 ,  G11C8/10 ,  G11C16/0458 ,  G11C16/08

摘要： In the present invention a bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.

摘要翻译： 在本发明中，描述了将数据和电压连接到双位闪存阵列的多个位线的位线解码器方案。 位线由第一解码器单元连接到多个中间数据线，并且中间数据线通过第二解码器单元连接到读出放大器的多个数据线。 在一个实施例中，电压通过单独的解码器单元连接到所选择的位线，并且在第二实施例中，电压通过连接到中间数据线的解码器单元连接。

公开(公告)号：US06535430B2

公开(公告)日：2003-03-18

申请号：US09785608

申请日：2001-02-16

申请人： Tomoko Ogura ,  Masaharu Kirihara

发明人： Tomoko Ogura ,  Masaharu Kirihara

IPC分类号： G11C1606

CPC分类号： G11C8/10 ,  G11C16/08

摘要： A wordline decoder for high density flash memory is described with negative voltage capability for memory operations such as erase. A main decoder is shared with a plurality of wordline driver circuits to reduce wiring congestion and overall layout size. In a second embodiment, a wordline decoder for fast read access is provided in which a high speed positive voltage decoder is separate from the negative voltage decoder with the addition of a triple well NMOS transistor into the inverter driver circuits. The use of triple well NMOS transistors reduces circuit and layout complexity.

摘要翻译： 描述了用于高密度闪存的字线解码器，其具有用于存储器操作（例如擦除）的负电压能力。 主解码器与多个字线驱动器电路共享以减少布线拥塞和整体布局尺寸。 在第二实施例中，提供了一种用于快速读取访问的字线解码器，其中高速正电压解码器与负电压解码器分离，并将三阱NMOS晶体管添加到反相器驱动器电路中。 使用三阱NMOS晶体管可以降低电路和布局的复杂性。

公开(公告)号：US07031192B1

公开(公告)日：2006-04-18

申请号：US10704437

申请日：2003-11-07

申请人： Ki-Tae Park ,  Tomoko Ogura

发明人： Ki-Tae Park ,  Tomoko Ogura

IPC分类号： G11C5/02

CPC分类号： G11C16/3445 ,  G11C16/0475 ,  G11C16/3436 ,  G11C16/3459

摘要： A data control unit is used to proved program, erase and verify signals to a non-volatile metal-oxide3-nitride-oxide-semiconductor (MONOS) memory. The data control unit comprises a plurality of sub-units that each contains a sense amplifier, two bi-directional flip-flop latches coupled in series and a program, erase and verify circuit. The two flip-flop latches each perform a task as a master latch or a slave latch depending on the memory operation. The program, erase and verify circuit in each sub-unit are connected together in a serial fashion such that multiple verification results are accumulated into one final result. Control signals are exchanged between a chip control unit and the data control unit to perform specified memory operations.

摘要翻译： 数据控制单元用于证明对非易失性金属氧化物氮化物 - 氧化物半导体（MONOS）存储器的编程，擦除和验证信号。 数据控制单元包括多个子单元，每个子单元包含读出放大器，串联耦合的两个双向触发器锁存器和编程，擦除和验证电路。 根据存储器操作，两个触发器锁存器各自执行作为主锁存器或从锁存器的任务。 每个子单元中的程序，擦除和验证电路以串行方式连接在一起，使多个验证结果累积成一个最终结果。 控制信号在芯片控制单元和数据控制单元之间交换以执行指定的存储器操作。

公开(公告)号：US06999345B1

公开(公告)日：2006-02-14

申请号：US10699331

申请日：2003-10-31

申请人： Ki-Tae Park ,  Tomoko Ogura

发明人： Ki-Tae Park ,  Tomoko Ogura

IPC分类号： G11C11/34

CPC分类号： G11C16/3459 ,  G11C16/3454

摘要： A method and circuit for verify and read of a nonvolatile memory cell without the use of a reference cell is described. The circuit comprises a sense amplifier that compares a voltage from the output of a read path of a selected bit line to a reference voltage. When the selected memory cell is erased, the bit line voltage is small pulling down the read path voltage below the reference voltage, which causes a sense amplifier output that is a logical “0”. When the selected cell has been programmed, the raise of the bit line voltage causes the bit line to be decoupled from the output of the read path. The read path output then continues to charge to a voltage higher than the reference voltage resulting in a logical “1” at the output of the sense amplifier.

摘要翻译： 描述了不使用参考单元来验证和读取非易失性存储单元的方法和电路。 电路包括读出放大器，其将来自所选位线的读取路径的输出的电压与参考电压进行比较。 当所选择的存储单元被擦除时，位线电压很小，将读取路径电压降低到低于参考电压，这导致逻辑“0”的读出放大器输出。 当所选择的单元被编程时，位线电压的升高使得位线与读路径的输出分离。 然后，读路径输出继续充电到高于参考电压的电压，从而在读出放大器的输出处产生逻辑“1”。

公开(公告)号：US06914791B1

公开(公告)日：2005-07-05

申请号：US10602228

申请日：2003-06-24

申请人： Ki-Tae Park ,  Shimeno Koji ,  Tomoko Ogura

发明人： Ki-Tae Park ,  Shimeno Koji ,  Tomoko Ogura

IPC分类号： H02M3/07

CPC分类号： H02M3/073

摘要： An improved charge pump circuit is provided using a triple-well structure where the charge pump circuit has a plurality of stages containing N-channel MOSFET devices in which each stage is contained in a P-well within a Deep N-well residing on a P-substrate. Each pump stage is formed in its own P-well and the pumping stages are serially connected from power supply source to the output terminal. Each pumping stage includes a charge transfer device, a first auxiliary device to precharge the gate of the charge transfer device with a voltage from the previous stage, and a second auxiliary device to switch coupling between the charge transfer device and its substrate region to reduce the body effect and increases the capacitive boosting effect. The multiple stages of circuitry are clocked from either a four-phase clock or a two-phase clock.

摘要翻译： 使用三阱结构提供了改进的电荷泵电路，其中电荷泵电路具有包含N沟道MOSFET器件的多个级，其中每个级包含在驻留在P上的深N阱内的P阱中 -基质。 每个泵级在其自己的P阱中形成，并且泵送级从电源连接到输出端。 每个泵送级包括电荷转移装置，用于从前一级的电压对电荷转移装置的栅极预充电的第一辅助装置和用于切换电荷转移装置与其衬底区域之间的耦合的第二辅助装置，以减少 身体效应并增加电容增强效果。 多级电路由四相时钟或两相时钟提供时钟。