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公开(公告)号：US07005386B1
公开(公告)日：2006-02-28
申请号：US10656467
申请日：2003-09-05
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , H01L21/0274 , H01L21/31058
摘要： According to one exemplary embodiment, a method for reducing resist height erosion in a gate etch process comprises a step of forming a first resist mask on an anti-reflective coating layer situated over a substrate, where the first resist mask has a first width. The anti-reflective coating layer may be, for example, an organic material. The method further comprises a step of trimming the first resist mask to form a second resist mask, where the second resist mask has a second width, and where the second width is less than the first width. The step of trimming the first resist mask may further comprise, for example, etching the anti-reflective coating layer. According to this exemplary embodiment, the method further comprises a step of performing an HBr plasma treatment on the second resist mask, wherein the HBr plasma treatment causes a vertical etch rate of the second resist mask to decrease.
摘要翻译： 根据一个示例性实施例，用于降低栅极蚀刻工艺中的抗蚀剂高度腐蚀的方法包括在位于衬底上的抗反射涂层上形成第一抗蚀剂掩模的步骤，其中第一抗蚀剂掩模具有第一宽度。 抗反射涂层可以是例如有机材料。 该方法还包括修整第一抗蚀剂掩模以形成第二抗蚀剂掩模的步骤，其中第二抗蚀剂掩模具有第二宽度，并且其中第二宽度小于第一宽度。 修整第一抗蚀剂掩模的步骤还可以包括例如蚀刻抗反射涂层。 根据该示例性实施例，该方法还包括在第二抗蚀剂掩模上执行HBr等离子体处理的步骤，其中HBr等离子体处理导致第二抗蚀剂掩模的垂直蚀刻速率降低。
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公开(公告)号：US06989332B1
公开(公告)日：2006-01-24
申请号：US10217730
申请日：2002-08-13
IPC分类号： H01L21/302
CPC分类号： H01L21/32139 , C23C16/26 , C23C16/56 , H01L21/0332
摘要： A method of manufacturing an integrated circuit includes providing a layer of polysilicon material above a semiconductor substrate. A layer of amorphous carbon is provided above the layer of polysilicon material and inert ions are implanted into the amorphous carbon layer. The layer of amorphous carbon is patterned to form an amorphous carbon mask, and a feature is formed in the layer of polysilicon according to the amorphous carbon mask.
摘要翻译： 一种制造集成电路的方法包括在半导体衬底之上提供多晶硅材料层。 在多晶硅材料层上方提供无定形碳层，惰性离子注入到无定形碳层中。 将非晶碳层图案化以形成无定形碳掩模，并且根据无定形碳掩模在多晶硅层中形成特征。
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53.发明申请Method of reducing STI divot formation during semiconductor device fabrication 有权在半导体器件制造期间减少STI纹路形成的方法公开(公告)号：US20050196928A1
公开(公告)日：2005-09-08
申请号：US10791759
申请日：2004-03-04
申请人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
发明人： Douglas Bonser , Johannes Groschopf , Srikanteswara Dakshina-Murthy , John Pellerin , Jon Cheek
IPC分类号： H01L21/3105 , H01L21/762 , H01L21/336
CPC分类号： H01L21/76224
摘要： STI divot formation is eliminated or substantially reduced by employing a very thin nitride polish stop layer, e.g., no thicker than 400 Å. The very thin nitride polish stop layer is retained in place during subsequent masking, implanting and cleaning steps to form dopant regions, and is removed prior to gate oxide and gate electrode formation.
摘要翻译： 通过使用非常薄的氮化物抛光停止层例如不厚于400来消除或显着降低STI纹线形成。 非常薄的氮化物抛光停止层在随后的掩模，注入和清洁步骤中保持就位以形成掺杂剂区域，并且在栅极氧化物和栅电极形成之前被去除。
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公开(公告)号：US06855627B1
公开(公告)日：2005-02-15
申请号：US10309923
申请日：2002-12-04
申请人： Srikanteswara Dakshina-Murthy , Scott A. Bell , Richard J. Huang , Richard C. Nguyen , Cyrus E. Tabery
发明人： Srikanteswara Dakshina-Murthy , Scott A. Bell , Richard J. Huang , Richard C. Nguyen , Cyrus E. Tabery
IPC分类号： H01L21/033 , H01L21/3213 , H01L21/4763
CPC分类号： H01L21/32139 , H01L21/0332
摘要： An exemplary embodiment relates to a method of using an amorphous carbon layer to prevent photoresist poisoning. The method includes doping a first amorphous carbon layer located above a substrate, providing an oxide layer above the first amorphous carbon layer where the oxide layer has a pinhole, and providing a second amorphous carbon layer adjacent to the oxide layer. The second amorphous carbon layer is undoped and the second amorphous carbon layer helps prevent photoresist poisoning.
摘要翻译： 示例性实施方案涉及使用无定形碳层以防止光致抗蚀剂中毒的方法。 该方法包括掺杂位于衬底上方的第一非晶碳层，在氧化物层具有针孔的第一非晶碳层之上提供氧化物层，并且提供与氧化物层相邻的第二非晶碳层。 第二非晶碳层未掺杂，第二非晶碳层有助于防止光致抗蚀剂中毒。
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55.发明授权Selective stress-inducing implant and resulting pattern distortion in amorphous carbon patterning 失效选择性应力诱导植入物和无定形碳图案化导致的图案变形公开(公告)号：US06825114B1
公开(公告)日：2004-11-30
申请号：US10424675
申请日：2003-04-28
IPC分类号： H01L2144
CPC分类号： H01L21/0332 , H01L21/32139 , H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： A method of forming a fuse for use in an integrated circuit using an amorphous carbon mask includes providing a mask material layer comprising amorphous carbon over a conductive layer. The mask material layer is doped with nitrogen, and an anti-reflective coating (ARC) feature is formed over the mask layer. A portion of the mask material layer is removed according to the ARC feature to form a mask, and the ARC feature is removed to form a warped mask. The conductive layer is patterned according to the warped mask, the warped mask is removed, and a silicide layer is provided over the patterned conductive layer.
摘要翻译： 使用非晶碳掩模形成用于集成电路的熔丝的方法包括在导电层上提供包含无定形碳的掩模材料层。 掩模材料层掺杂有氮，并且在掩模层上形成抗反射涂层（ARC）特征。 根据ARC特征去除掩模材料层的一部分以形成掩模，并且去除ARC特征以形成翘曲的掩模。 根据翘曲的掩模对导电层进行图案化，去除翘曲的掩模，并且在图案化的导电层上提供硅化物层。
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56.发明授权公开(公告)号：US06673635B1
公开(公告)日：2004-01-06
申请号：US10185780
申请日：2002-06-28
IPC分类号： H01L2100
CPC分类号： H01L23/544 , H01L21/30604 , H01L21/3083 , H01L21/31116 , H01L21/31144 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： Methods are presented for fabrication of alignment features of a desired depth, and shallow trench isolation (STI) features in Silicon-On-Insulator (SOI) material. Specific embodiments require no more than two lithography and etch processes, which represents an improvement over current methodology requiring three lithography and etch processes in order to produce the desired features during manufacture of a semiconductor device.
摘要翻译： 提出了用于制造所需深度的对准特征以及绝缘体上硅（SOI）材料中的浅沟槽隔离（STI）特征的方法。 具体实施方案要求不超过两个光刻和蚀刻工艺，其代表了需要三次光刻和蚀刻工艺的电流方法的改进，以便在制造半导体器件期间产生期望的特征。
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57.发明授权Method of using amorphous carbon film as a sacrificial layer in replacement gate integration processes 有权在替代栅极集成工艺中使用无定形碳膜作为牺牲层的方法公开(公告)号：US06664154B1
公开(公告)日：2003-12-16
申请号：US10185320
申请日：2002-06-28
IPC分类号： H01L21336
CPC分类号： H01L29/66545 , H01L21/28079 , H01L21/28097 , H01L29/495 , H01L29/4975
摘要： An exemplary embodiment relates to a method of using amorphous carbon in replacement gate integration processes. The method can include depositing an amorphous carbon layer above a substrate, patterning the amorphous carbon layer, depositing a dielectric layer over the patterned amorphous carbon layer, removing a portion of the deposited dielectric layer to expose a top of the patterned amorphous carbon layer, removing the patterned amorphous carbon layer leaving an aperture in the dielectric layer, and forming a metal gate in the aperture of the dielectric layer.
摘要翻译： 示例性实施方案涉及在替代栅极整合方法中使用无定形碳的方法。 该方法可以包括在衬底上沉积无定形碳层，图案化无定形碳层，在图案化的非晶碳层上沉积介电层，去除沉积的介电层的一部分以暴露图案化的无定形碳层的顶部，去除 图案化的非晶碳层在电介质层中留下孔，并在电介质层的孔中形成金属栅极。
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公开(公告)号：US06596553B1
公开(公告)日：2003-07-22
申请号：US10180141
申请日：2002-06-26
IPC分类号： H01L2166
CPC分类号： H01L22/24
摘要： An exemplary embodiment relates to a method of pinhole decoration and detection. The method can include providing a material layer above an amorphous carbon layer where the material layer has a pinhole, providing a film over the material layer where the film has a substantially planar surface except above the pinhole, and detecting the pinhole by detecting a non-planar location on the substantially planar surface of the film.
摘要翻译： 示例性实施例涉及针孔装饰和检测的方法。 该方法可以包括在无定形碳层上方提供材料层，其中材料层具有针孔，在材料层上提供膜，其中膜具有除了针孔之外的基本平坦的表面，并且通过检测非针状孔来检测针孔， 在薄膜的基本平坦的表面上的平面位置。
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59.发明授权System and method for imprint lithography to facilitate dual damascene integration with two imprint acts 有权用于压印光刻的系统和方法，以促进双重镶嵌与两个印记动作的整合公开(公告)号：US08007631B2
公开(公告)日：2011-08-30
申请号：US11741991
申请日：2007-04-30
CPC分类号： H01L21/76817 , B82Y10/00 , B82Y40/00 , G03F7/0002 , H01L21/31144 , H01L21/76811
摘要： A system and method are provided to facilitate dual damascene interconnect integration with two imprint acts. The method provides for creation of a pair of translucent imprint molds containing the dual damascene pattern to be imprinted. The first imprint mold of the pair contains the via features of the dual damascene pattern and the second imprint mold of the pair contains the trench features. The via feature imprint mold is brought into contact with a first imaging layer deposited upon a first transfer layer which is deposited upon a dielectric layer of a substrate. The trench feature imprint mold is brought into contact with a second imaging layer deposited upon a second transfer layer which is deposited upon the first imaging layer of the substrate. When each imaging layer is exposed to a source of illumination, it cures with a structure matching the features of the corresponding imprint mold. A sequence of etches transfer and combine the via features from the first imaging layer with the trenches from the second imaging layer to create the dual damascene openings within the dielectric layer.
摘要翻译： 提供了一种系统和方法来促进与两个印记动作的双镶嵌互连集成。 该方法提供了一对包含要印制的双镶嵌图案的半透明压印模具。 该对的第一压印模具包含双镶嵌图案的通孔特征，并且该对的第二压印模具包含沟槽特征。 通孔特征压印模具与沉积在沉积在基板的电介质层上的第一转印层上的第一成像层接触。 沟槽特征压印模具与沉积在沉积在基板的第一成像层上的第二转印层上的第二成像层接触。 当每个成像层暴露于照明源时，它将以匹配相应压印模具的特征的结构固化。 一系列蚀刻将来自第一成像层的通孔特征与来自第二成像层的沟槽结合，以在介电层内形成双镶嵌开口。
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公开(公告)号：US07384569B1
公开(公告)日：2008-06-10
申请号：US10909464
申请日：2004-08-02
CPC分类号： G03F7/0002 , B82Y10/00 , B82Y40/00
摘要： Disclosed are photolithographic systems and methods, and more particularly systems and methodologies that enhance imprint mask feature resolution. An aspect generates feedback information that facilitates control of imprint mask feature size and resolution via employing a scatterometry system to detect resolution enhancement need, and decreasing imprint mask feature size and increasing resolution of the imprint mask via a trim etch procedure.
摘要翻译： 公开了光刻系统和方法，更具体地说，增强了印迹掩模特征分辨率的系统和方法。 方面产生反馈信息，其通过采用散射测量系统来检测分辨率增强需求，以及通过修剪蚀刻程序减小压印掩模特征尺寸并增加印迹掩模的分辨率，从而有助于控制印迹掩模特征尺寸和分辨率。
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