公开(公告)号：US20090141568A1

公开(公告)日：2009-06-04

申请号：US12055095

申请日：2008-03-25

申请人： Subramani Kengeri ,  Kuoyuan Peter Hsu ,  Bing Wang

发明人： Subramani Kengeri ,  Kuoyuan Peter Hsu ,  Bing Wang

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/4094 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2207/104

摘要： A method of operating a memory circuit includes providing the memory circuit. The memory circuit includes a memory cell; a word line connected to the memory cell; a first local bit line and a second local bit line connected to the memory cell; and a first global bit line and a second global bit line coupled to the first and the second local bit lines, respectively. The method further includes starting an equalization to equalize voltages on the first and the second local bit lines; stopping the equalization; and after the step of starting the equalization and before the step of stopping the equalization, writing values from the first and the second global bit lines to the first and the second local bit lines.

摘要翻译： 一种操作存储电路的方法包括提供存储电路。 存储电路包括存储单元; 连接到存储单元的字线; 连接到存储单元的第一局部位线和第二局部位线; 以及分别耦合到第一和第二局部位线的第一全局位线和第二全局位线。 该方法还包括开始均衡以均衡第一和第二局部位线上的电压; 停止均衡 并且在开始均衡的步骤之后，在停止均衡的步骤之前，将值从第一和第二全局位线写入第一和第二局部位线。

公开(公告)号：US07251186B1

公开(公告)日：2007-07-31

申请号：US11147928

申请日：2005-06-07

申请人： Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Shreekanth Sampigethaya ,  Sanjiv Kainth

发明人： Subramani Kengeri ,  Deepak Sabharwal ,  Prakash Bhatia ,  Shreekanth Sampigethaya ,  Sanjiv Kainth

IPC分类号： G11C7/00

CPC分类号： G11C7/1075

摘要： A multi-port memory device with an array of single-port memory cells is disclosed. According to one embodiment of the invention, the multi-port memory device has N number of memory ports, and is capable of performing any combination of N number of read/write operations during a single cycle of an externally generated core clock signal, without the need of any other externally generated clocking signals.

摘要翻译： 公开了具有单端口存储器单元阵列的多端口存储器件。 根据本发明的一个实施例，多端口存储器件具有N个存储器端口，并且能够在外部产生的核心时钟信号的单个周期期间执行N个读/写操作的任何组合，而没有 需要任何其他外部产生的时钟信号。

公开(公告)号：US07200793B1

公开(公告)日：2007-04-03

申请号：US10106305

申请日：2002-03-22

申请人： Subramani Kengeri ,  David Walter Carr ,  Paul Nadj ,  Jaya Prakash Samala

发明人： Subramani Kengeri ,  David Walter Carr ,  Paul Nadj ,  Jaya Prakash Samala

IPC分类号： G11C29/00

CPC分类号： G06F11/1064 ,  G11C2029/0411

摘要： Error checking and correcting (ECC) is performed on data held in a content addressable memory. An error check circuit receives words from a memory circuit or circuits, generates an error status and generates a corrected value when appropriate. A control circuit sequences through each of the words of the memory circuit(s), periodically reads from the memory circuit the next word in the sequence and provides the next word to the error check circuit. The bandwidth consumed by the periodic error check phase can be controlled by adjusting the interval between reads.

摘要翻译： 对内容可寻址存储器中保存的数据执行错误检查和校正（ECC）。 错误检查电路从存储器电路或电路接收字，产生错误状态并在适当时产生校正值。 控制电路通过存储器电路的每一个字序列，周期性地从存储器电路读取序列中的下一个字，并将下一个字提供给错误校验电路。 可以通过调整读取间隔来控制周期性错误检查阶段消耗的带宽。

公开(公告)号：US06459647B1

公开(公告)日：2002-10-01

申请号：US09778380

申请日：2001-02-06

申请人： Subramani Kengeri

发明人： Subramani Kengeri

IPC分类号： G11C800

CPC分类号： G11C8/12 ,  G11C5/063 ,  G11C7/1072

摘要： Apparatus, methods, and systems are disclosed for providing a memory device, such as a SDRAM, having distributed memory bank segments logically coupled to form a virtual memory bank. Each of the memory bank segments are proximally positioned relative to associated I/Os. In this way, the delay times from each of the memory bank segments to their respective I/Os are substantially equal to each other. In addition, the proximal positioning of the memory banks results in reduced signal delays due to reduced signal paths from each bank segment and respective I/O.

摘要翻译： 公开了用于提供诸如SDRAM的存储器件，其具有逻辑耦合以形成虚拟存储体的分布式存储体区段的装置，方法和系统。 每个存储体段相对于相关联的I / O向近侧定位。 以这种方式，从每个存储体段到它们各自的I / O的延迟时间基本上彼此相等。 此外，由于来自每个存储体段的信号路径减少和相应的I / O，存储体组的近端定位导致信号延迟减小。

公开(公告)号：US5831315A

公开(公告)日：1998-11-03

申请号：US795062

申请日：1997-02-05

申请人： Subramani Kengeri ,  Chitranjan N. Reddy

发明人： Subramani Kengeri ,  Chitranjan N. Reddy

IPC分类号： H01L27/11 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC分类号： H01L27/1112

摘要： An SRAM array configuration is disclosed. SRAM cells (102) are arranged in rows and columns. Cell rows (104a-104f) are each driven by a particular word line (132). Cell row pairs (108a and 108b) are supplied with a low power supply voltage (Vss) by a number of Vss connections 116 disposed parallel to the cell rows (104a-104f). The word lines (132) and Vss connections 116 are "strapped" by low resistance word line straps (110b-110e) and Vss straps (112a-112b). Both the word line straps (110b-110e) and the Vss straps (112a-112b) are substantially offset with respect to their associated word lines (132) and Vss connections 116, respectively. The Vss strap offset is accomplished with the use of a Vss line 140 that makes contact with the Vss connections 116 and further includes landing portions 120 which extend in the column direction and make contact with the Vss straps (112a-112b).

摘要翻译： 公开了SRAM阵列配置。 SRAM单元（102）以行和列排列。 单元行（104a-104f）分别由特定字线（132）驱动。 通过与单元行（104a-104f）平行设置的多个Vss连接116，向单元行对（108a和108b）提供低电源电压（Vss）。 字线（132）和Vss连接116被低电阻字线带（110b-110e）和Vss带（112a-112b）“捆绑”。 字线条（110b-110e）和Vss带（112a-112b）分别相对于它们相关联的字线（132）和Vss连接116基本偏移。 Vss带偏移通过使用与Vss连接116接触的Vss线140并且还包括在列方向上延伸并与Vss带（112a-112b）接触的着陆部分120来实现。

公开(公告)号：US5717645A

公开(公告)日：1998-02-10

申请号：US797810

申请日：1997-02-07

申请人： Subramani Kengeri ,  Chitranjan N. Reddy

发明人： Subramani Kengeri ,  Chitranjan N. Reddy

IPC分类号： G11C5/02 ,  G11C11/409 ,  G11C13/00

CPC分类号： G11C5/025 ,  G11C11/409

摘要： A random access memory (RAM) (10) is disclosed. A network of driver lines (28) extends over a number of core arrays (12a-12p) connecting a control bank 24 with column decode banks (26a and 26b), and the column decode banks (26a and 26b) with sense banks 46 within the core arrays (12a-12p). The driver lines 28 include predecode lines 30 and clock lines 32 for coupling predecode signals and clock signals from the control bank 24 to the column decode banks (26a and 26b). In addition, the driver lines 28 include column select lines 34 and sense driver lines 36 for coupling column select signals and sense amplifier enable signals from the column decode banks (26a and 26b) to the sense banks 46. The sense banks 46 include sense amplifiers 80 that are shared between array quadrants 42 by decoded transfer gate banks (70a and 70b). Advantageous placement of precharge circuits 82 and equalization circuits 86 provides a compact sense bank structure 46.

摘要翻译： 公开了一种随机存取存储器（RAM）（10）。 驱动器线路（28）的网络在连接控制组24与列解码组（26a和26b）的多个核心阵列（12a-12p）​​之间延伸，并且列解码组（26a和26b）与有义组46 芯阵列（12a-12p）​​。 驱动器线路28包括用于将来自控制组24的预解码信号和时钟信号耦合到列解码组（26a和26b）的预解码线30和时钟线32。 此外，驱动器线28包括列选择线34和感测驱动器线36，用于将列选择信号和来自列解码组（26a和26b）的读出放大器使能信号耦合到感测组46.感测组46包括读出放大器 80，其被解码的传输门库（70a和70b）在阵列象限42之间共享。 预充电电路82和均衡电路86的有利位置提供了紧凑的感测组结构46。