公开(公告)号：US11093684B2

公开(公告)日：2021-08-17

申请号：US16659305

申请日：2019-10-21

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Jung-Chan Yang ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Chi-Yu Lu

IPC: G06F30/00 ,  G06F30/398 ,  G03F1/70 ,  G03F1/36 ,  G06F30/30 ,  G06F30/3953 ,  G06F119/18

Abstract: A method for designing an integrated circuit includes steps of selecting a power rail of a cell, determining that a clearance distance for an electrical connection to or around the power rail is not sufficient to fit the electrical connection, selecting a power rail portion of the power rail for modification, and modifying a shape of the power rail portion to provide a clearance distance sufficient to fit the electrical connection. As clearance distances between features in an interconnection structure of an integrated circuit become smaller, manufacturing becomes more difficult and error-prone. Increasing clearance distances improves manufacturability of an integrated circuit. Modifying the shape of an integrated circuit power rail increases clearance distance to and/or around a power rail.

公开(公告)号：US11024622B2

公开(公告)日：2021-06-01

申请号：US16722324

申请日：2019-12-20

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F30/39 ,  G06F30/392 ,  G06F30/398 ,  H01L23/528 ,  H01L27/092

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated in the first direction, and a second gate electrode structure having a third portion and a fourth portion separated in the first direction. The integrated circuit further includes a conductive feature including a first section electrically connected to the second portion, wherein the first section extends in the second direction, a second section electrically connected to the third portion, wherein the second section extends in the second direction, and a third section electrically connecting the first section and the second section, the third section extends in a third direction angled with respect to the first and second directions.

公开(公告)号：US10970451B2

公开(公告)日：2021-04-06

申请号：US16553958

申请日：2019-08-28

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Jian-Sing Li ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Jung-Chan Yang ,  Li-Chun Tien ,  Ting Yu Chen ,  Tzu-Ying Lin

IPC: G06F30/392 ,  H01L27/02

Abstract: A method includes positioning a first active region adjacent to a pair of second active regions in an initial integrated circuit (IC) layout diagram of an initial cell, to align side edges of the first active region and corresponding side edges of each second active region of the pair of second active regions along a cell height direction. The method further includes arranging at least one first fin feature in the first active region, to obtain a modified cell having a modified IC layout diagram. The side edges of the first active region and the corresponding side edges of each second active region extend along the cell height direction. A height dimension of the first active region in the cell height direction is less than half of a height dimension of each second active region of the pair of second active regions in the cell height direction. At least one of the positioning the first active region or the arranging the at least one first fin feature is executed by a processor.

公开(公告)号：US10950594B2

公开(公告)日：2021-03-16

申请号：US16420919

申请日：2019-05-23

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chung-Te Lin ,  Ting-Wei Chiang ,  Hui-Zhong Zhuang ,  Pin-Dai Sue ,  Li-Chun Tien

IPC: H01L27/02 ,  G06F30/392 ,  H01L27/092 ,  H01L29/423 ,  H01L27/118

Abstract: A layout includes a plurality of cells and at least one dummy gate electrode continuously extends across the cells. Since the dummy gate electrode is electrically conductive, the dummy gate electrode can be utilized for interconnecting the cells. That is, some signals may travel through the dummy gate electrode rather than through a metal one line or a metal two line. Therefore, an amount of metal one lines and/or metal two lines for interconnecting the cells can be reduced.

公开(公告)号：US10522527B2

公开(公告)日：2019-12-31

申请号：US15233126

申请日：2016-08-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Hui-Zhong Zhuang ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: G06F17/50 ,  H01L27/02 ,  H01L23/528 ,  H01L27/092

Abstract: An integrated circuit includes a plurality of gate electrode structures extending along a first direction and having a predetermined spatial resolution measurable along a second direction orthogonal to the first direction. The plurality of gate electrode structures includes a first gate electrode structure having a first portion and a second portion separated by a first carve-out region, and a conductive feature over the first carve-out region and electrically connecting the first portion and the second portion of the first gate electrode.

公开(公告)号：US10163883B2

公开(公告)日：2018-12-25

申请号：US15183112

申请日：2016-06-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Cheok-Kei Lei ,  Yu-Chi Li ,  Chia-Wei Tseng ,  Zhe-Wei Jiang ,  Chi-Lin Liu ,  Jerry Chang-Jui Kao ,  Jung-Chan Yang ,  Chi-Yu Lu ,  Hui-Zhong Zhuang

IPC: G06F17/50 ,  H01L23/50 ,  H01L27/02 ,  H01L23/528 ,  H01L23/532

Abstract: A layout method includes: selecting, by a processor or manual, a first layout device in a layout of an integrated circuit; selecting a second device abutting the first layout device at a boundary between the first layout device and the second layout device, wherein a conductive path is disposed across the boundary of the first layout device and the second layout device; and disposing a cut layer on the conductive path and nearby the boundary. The first layout device is a first layout pattern and the second layout device is a second layout pattern different from the first layout pattern.

公开(公告)号：US09679915B2

公开(公告)日：2017-06-13

申请号：US14876123

申请日：2015-10-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo ,  Ho-Chieh Hsieh ,  Hui-Zhong Zhuang ,  Kuo-Feng Tseng ,  Lee-Chung Lu ,  Cheng-Chung Lin ,  Sang Hoo Dhong

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/1189

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

公开(公告)号：US09659129B2

公开(公告)日：2017-05-23

申请号：US14253205

申请日：2014-04-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Shang-Chih Hsieh ,  Hui-Zhong Zhuang ,  Ting-Wei Chiang ,  Chun-Fu Chen ,  Hsiang-Jen Tseng

IPC: H01L23/50 ,  G06F17/50 ,  H01L21/768 ,  H01L27/118 ,  H01L27/02

CPC classification number: G06F17/5072 ,  H01L21/768 ,  H01L27/0207 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An integrated circuit, manufactured by a process having a nominal minimum pitch of metal lines, includes a plurality of metal lines and a plurality of standard cells under the plurality of metal lines. The plurality of metal lines extends along a first direction, and the plurality of metal lines are separated, in a second direction perpendicular to the first direction, by integral multiples of the nominal minimum pitch. At least one of the plurality of standard cells has a cell height along the second direction, and the cell height is a non-integral multiple of the nominal minimum pitch.

公开(公告)号：US20160254190A1

公开(公告)日：2016-09-01

申请号：US15150149

申请日：2016-05-09

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: H01L21/8234 ,  H01L21/304 ,  H01L29/66

CPC classification number: H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Abstract translation: 公开了一种形成用于制造集成电路（IC）的布局设计的方法。 该方法包括识别由布局设计的多个门结构布局图案的一个或多个段所占据的布局设计中的一个或多个区域; 以及生成与所识别的一个或多个区域重叠的一组布局模式。 多个栅极结构布局图案具有比预定光刻技术的空间分辨率小的预定间距。 布置图案集合的第一布局图案具有小于预定间距的两倍的宽度。

公开(公告)号：US09336348B2

公开(公告)日：2016-05-10

申请号：US14484588

申请日：2014-09-12

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tung-Heng Hsieh ,  Chung-Te Lin ,  Sheng-Hsiung Wang ,  Hui-Zhong Zhuang ,  Min-Hsiung Chiang ,  Ting-Wei Chiang ,  Li-Chun Tien

IPC: G06F17/50

CPC classification number: H01L21/82345 ,  G06F17/5072 ,  H01L21/3043 ,  H01L21/32139 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of forming a layout design for fabricating an integrated circuit (IC) is disclosed. The method includes identifying one or more areas in the layout design occupied by one or more segments of a plurality of gate structure layout patterns of the layout design; and generating a set of layout patterns overlapping the identified one or more areas. The plurality of gate structure layout patterns has a predetermined pitch smaller than a spatial resolution of a predetermined lithographic technology. A first layout pattern of the set of layout patterns has a width less than twice the predetermined pitch.

Abstract translation: 公开了一种形成用于制造集成电路（IC）的布局设计的方法。 该方法包括识别由布局设计的多个门结构布局图案的一个或多个段所占据的布局设计中的一个或多个区域; 以及生成与所识别的一个或多个区域重叠的一组布局模式。 多个栅极结构布局图案具有比预定光刻技术的空间分辨率小的预定间距。 布置图案集合的第一布局图案具有小于预定间距的两倍的宽度。