公开(公告)号：US20150131077A1

公开(公告)日：2015-05-14

申请号：US14604488

申请日：2015-01-23

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo ,  Ping-Lin Yang ,  Cheng-Chung Lin ,  Osamu Takahashi ,  Sang Hoo Dhong

IPC: H01J37/317

CPC classification number: H01J37/3175 ,  H01J37/3023 ,  H01J37/3177 ,  H01J2237/2485 ,  H01J2237/31762

Abstract: An embodiment of a method of lithography includes generating a beam of electrons. A first pixel and a second pixel are each configured to pattern the beam. Using time domain multiplex loading, the first and second pixels are controlled such that the beam is patterned. The patterning includes receiving a first clock signal and using the first clock signal to generate a second clock signal and a third clock signal. The second clock signal is sent to the first pixel and sending the third clock signal is sent to the second pixel.

Abstract translation: 光刻方法的一个实施例包括产生电子束。 第一像素和第二像素都被配置为对光束进行图案化。 使用时域多路复用加载，控制第一和第二像素使得光束被图案化。 图案化包括接收第一时钟信号并使用第一时钟信号产生第二时钟信号和第三时钟信号。 第二时钟信号被发送到第一像素，并且发送第三时钟信号被发送到第二像素。

公开(公告)号：US20130149856A1

公开(公告)日：2013-06-13

申请号：US13728833

申请日：2012-12-27

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chung Lin ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC: H01L21/768

CPC classification number: H01L21/76885 ,  H01L23/53228 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0381 ,  H01L2224/0401 ,  H01L2224/05027 ,  H01L2224/05166 ,  H01L2224/05181 ,  H01L2224/05187 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/81013 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/10336 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/00 ,  H01L2224/05552

Abstract: An integrated circuit device is disclosed. An exemplary integrated circuit device includes a first copper layer, a second copper layer, and an interface between the first and second copper layers. The interface includes a flat zone interface region and an intergrowth interface region, wherein the flat zone interface region is less than or equal to 50% of the interface.

Abstract translation: 公开了一种集成电路器件。 示例性的集成电路器件包括第一铜层，第二铜层以及第一和第二铜层之间的界面。 该界面包括平坦区域界面区域和共同生长界面区域，其中平坦区域界面区域小于或等于界面的50％。

公开(公告)号：US09286970B2

公开(公告)日：2016-03-15

申请号：US14326124

申请日：2014-07-08

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Zhang Kuo ,  Cheng-Chung Lin ,  Ho-Chieh Hsieh ,  Kuo Feng Tseng ,  Sang Hoo Dhong

IPC: G11C11/417 ,  G11C5/02 ,  G11C11/4076 ,  G11C5/06 ,  G11C7/00 ,  G11C7/08 ,  G11C11/419 ,  G11C5/14 ,  G11C11/4094 ,  G11C7/12

CPC classification number: G11C11/419 ,  G11C5/025 ,  G11C5/06 ,  G11C5/148 ,  G11C7/08 ,  G11C7/12 ,  G11C11/4076 ,  G11C11/4094 ,  G11C11/417

Abstract: A memory includes a word line, a bit line and a complementary bit line. A memory cell has a data node coupled to the bit line and a complementary data node coupled to the complementary bit line. The word line controls access to the memory cell. A circuit is coupled to the bit line and the complementary bit line. The circuit is configured to pull up to a high voltage, pull down to a low voltage, or float the bit line and the complementary bit line based on a first timing of pre-charging and a second timing of write driving. The first timing and the second timing are synchronized.

Abstract translation: 存储器包括字线，位线和互补位线。 存储器单元具有耦合到位线的数据节点和耦合到互补位线的互补数据节点。 字线控制对存储单元的访问。 电路耦合到位线和互补位线。 该电路被配置为基于预充电的第一定时和写入驱动的第二定时上拉至高电压，下拉至低电压或浮动位线和互补位线。 第一定时和第二定时同步。

公开(公告)号：US20140151878A1

公开(公告)日：2014-06-05

申请号：US14175668

申请日：2014-02-07

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chung Lin ,  Hsiu-Jen Lin ,  Cheng-Ting Chen ,  Chun-Cheng Lin ,  Ming-Da Cheng ,  Chung-Shi Liu

IPC: H01L23/00

CPC classification number: H01L24/14 ,  H01L23/49816 ,  H01L23/5389 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16225 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/01322 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/15787 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00

Abstract: A fine pitch package-on-package (PoP), and a method of forming, are provided. The PoP may be formed by placing connections, e.g., solder balls, on a first substrate having a semiconductor die attached thereto. A first reflow process is performed to elongate the solder balls. Thereafter, a second substrate having another semiconductor die attached thereto is connected to the solder balls. A second reflow process is performed to form an hourglass connection.

Abstract translation: 提供了一种精细节距封装（PoP）和一种形成方法。 PoP可以通过将连接例如焊球放置在具有附接到其上的半导体管芯的第一基板上而形成。 执行第一回流处理以延长焊球。 此后，具有安装有另一个半导体管芯的第二基板连接到焊球。 执行第二回流处理以形成沙漏连接。

公开(公告)号：US11270052B2

公开(公告)日：2022-03-08

申请号：US17021702

申请日：2020-09-15

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.

Inventor： Chia Hao Tu ,  Hsueh-Chih Chou ,  Sang Hoo Dhong ,  Jerry Chang Jui Kao ,  Chi-Lin Liu ,  Cheng-Chung Lin ,  Shang-Chih Hsieh

IPC: G06F30/3312 ,  G06F1/14

Abstract: A method includes: receiving a library associated with a cell; determining a plurality of candidate hold times for the cell; acquiring a plurality of candidate setup times corresponding to the plurality of candidate hold times, wherein a data delay associated with each of the candidate setup time fulfills a data delay constraint for the cell; adding the plurality of candidate setup times to the plurality of candidate hold times, respectively, to obtain a plurality of candidate time windows; and selecting a target time window having a minimal time span among the candidate time windows. At least one of the receiving, determining, acquiring, adding and selecting steps is conducted by at least one processor.

公开(公告)号：US09679915B2

公开(公告)日：2017-06-13

申请号：US14876123

申请日：2015-10-06

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo ,  Ho-Chieh Hsieh ,  Hui-Zhong Zhuang ,  Kuo-Feng Tseng ,  Lee-Chung Lu ,  Cheng-Chung Lin ,  Sang Hoo Dhong

IPC: H01L27/118

CPC classification number: H01L27/11807 ,  H01L2027/11855 ,  H01L2027/11861 ,  H01L2027/1189

Abstract: An integrated circuit comprises standard cells arranged in rows and columns. The integrated circuit also comprises tap cells arranged in rows and columns. The tap cells each comprise a substrate having a first dopant type and a thickness from a first surface of the substrate to a second surface of the substrate. The integrated circuit further comprises a well region in the substrate having a second dopant type different from the first dopant type and a depth from the first surface of the substrate less than the thickness of the substrate. The integrated circuit additionally comprises a first quantity of rows of tap cells and a second quantity of rows of tap cells less than the first quantity. Each row of the first quantity of rows of tap cells comprises at least one well contact, and each row of tap cells of the second quantity of tap cells comprises at least one substrate contact.

公开(公告)号：US09449931B2

公开(公告)日：2016-09-20

申请号：US14468236

申请日：2014-08-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Chung Lin ,  Chung-Shi Liu ,  Meng-Wei Chou ,  Kuo Cheng Lin ,  Wen-Hsiung Lu ,  Chien Ling Hwang ,  Ying-Jui Huang ,  De-Yuan Lu

IPC: H01L21/44 ,  H01L21/4763 ,  H01L23/00 ,  H01L23/488 ,  H01L21/321 ,  H01L21/02 ,  H01L21/768

CPC classification number: H01L24/11 ,  H01L21/02052 ,  H01L21/32125 ,  H01L21/76873 ,  H01L21/76885 ,  H01L23/488 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2221/1084 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05073 ,  H01L2224/05541 ,  H01L2224/05573 ,  H01L2224/1111 ,  H01L2224/1132 ,  H01L2224/1145 ,  H01L2224/11452 ,  H01L2224/1146 ,  H01L2224/11462 ,  H01L2224/11464 ,  H01L2224/11472 ,  H01L2224/11474 ,  H01L2224/11614 ,  H01L2224/1181 ,  H01L2224/11849 ,  H01L2224/11903 ,  H01L2224/1191 ,  H01L2224/11912 ,  H01L2224/13005 ,  H01L2224/13017 ,  H01L2224/13018 ,  H01L2224/1308 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/13084 ,  H01L2224/13111 ,  H01L2224/13116 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/13164 ,  H01L2224/81191 ,  H01L2924/00013 ,  H01L2924/01006 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01059 ,  H01L2924/01072 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/014 ,  H01L2924/0541 ,  H01L2924/07025 ,  H01L2924/10329 ,  H01L2924/14 ,  H01L2924/20102 ,  H01L2924/3512 ,  H01L2924/381 ,  H01L2924/3841 ,  H01L2924/0105 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2924/207

Abstract: Apparatus and methods for providing solder pillar bumps. Pillar bump connections are formed on input/output terminals for integrated circuits by forming a pillar of conductive material using plating of a conductive material over terminals of an integrated circuit. A base portion of the pillar bump has a greater width than an upper portion. A cross-section of the base portion of the pillar bump may make a trapezoidal, rectangular, or sloping shape. Solder material may be formed on the top surface of the pillar. The resulting solder pillar bumps form fine pitch package solder connections that are more reliable than those of the prior art.

Abstract translation: 用于提供焊料柱凸块的装置和方法。 通过在集成电路的端子上形成导电材料的电镀，形成导电材料的柱，形成用于集成电路的输入/输出端子上的柱凸起连接。 柱状凸块的基部具有比上部更大的宽度。 柱形凸起的基部的横截面可以形成梯形，矩形或倾斜的形状。 焊料可以形成在柱的顶表面上。 所得到的焊料柱凸起形成比现有技术更可靠的细间距封装焊接连接。

公开(公告)号：US09202662B2

公开(公告)日：2015-12-01

申请号：US13756178

申请日：2013-01-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Jimmy Hsiao ,  Ming-Zhang Kuo ,  Ping-Lin Yang ,  Cheng-Chung Lin ,  Osamu Takahashi ,  Sang Hoo Dhong

IPC: G21K5/04 ,  H01J29/62 ,  H01J3/12 ,  H01J3/16 ,  H01J3/18 ,  H01J37/30 ,  H01J37/317

CPC classification number: H01J29/62 ,  H01J3/12 ,  H01J3/16 ,  H01J3/18 ,  H01J37/3007 ,  H01J37/3177 ,  H01J2237/1205 ,  H01J2237/31789

Abstract: A system includes an integrated circuit (IC) design data base having a feature, a source configured to generate a radiation beam, a pattern generator (PG) including a mirror array plate and an electrode plate disposed over the mirror array plate, wherein the electrode plate includes a lens let having a first dimension and a second dimension perpendicular to the first dimension with the first dimension larger than the second dimension so that the lens let modifies the radiation beam to form the long shaped radiation beam, and a stage configured secured the substrate. The system further includes an electric field generator connecting the mirror array plate. The mirror array plate includes a mirror. The mirror absorbs or reflects the radiation beam. The radiation beam includes electron beam or ion beam. The second dimension is equal to a minimum dimension of the feature.

Abstract translation: 一种系统包括具有特征的集成电路（IC）设计数据库，被配置为产生辐射束的源，包括反射镜阵列板的图案发生器（PG）和设置在所述反射镜阵列板上的电极板，其中所述电极 板包括透镜，其具有垂直于第一尺寸的第一尺寸和第二尺寸，其第一尺寸大于第二尺寸，使得透镜使得辐射束修改以形成长形辐射束，并且被配置为将 基质。 该系统还包括连接镜阵列板的电场发生器。 镜阵列板包括镜子。 镜子吸收或反射辐射束。 辐射束包括电子束或离子束。 第二个维度等于该特征的最小尺寸。

公开(公告)号：US08941085B2

公开(公告)日：2015-01-27

申请号：US13914118

申请日：2013-06-10

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Ming-Zhang Kuo ,  Ping-Lin Yang ,  Cheng-Chung Lin ,  Osamu Takahashi ,  Sang Hoo Dhong

IPC: G21K5/04 ,  G03F7/20

CPC classification number: H01J37/3175 ,  H01J37/3023 ,  H01J37/3177 ,  H01J2237/2485 ,  H01J2237/31762

Abstract: The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Abstract translation: 本公开提供了用于电子束光刻的系统和方法。 一个系统包括可操作以产生光束的电子源和可操作以对光束进行图案化的像素阵列。 控制电路与像素阵列间隔一段距离并耦合到像素阵列。 控制电路使用时域多路复用加载（TMDL）来控制像素阵列。

公开(公告)号：US20140268078A1

公开(公告)日：2014-09-18

申请号：US13914118

申请日：2013-06-10

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Ming-Zhang Kuo ,  Ping-Lin Yang ,  Cheng-Chung Lin ,  Osamu Takahashi ,  Sang Hoo Dhong

IPC: G03F7/20

CPC classification number: H01J37/3175 ,  H01J37/3023 ,  H01J37/3177 ,  H01J2237/2485 ,  H01J2237/31762

Abstract: The present disclosure provides a systems and methods for e-beam lithography. One system includes an electron source operable to produce a beam and an array of pixels operable to pattern the beam. Control circuitry is spaced a distance from and coupled to the array of pixels. The control circuitry uses time domain multiplex loading (TMDL) to control the array of pixels.

Abstract translation: 本公开提供了用于电子束光刻的系统和方法。 一个系统包括可操作以产生光束的电子源和可操作以对光束进行图案化的像素阵列。 控制电路与像素阵列间隔一段距离并耦合到像素阵列。 控制电路使用时域多路复用加载（TMDL）来控制像素阵列。