公开(公告)号：US11853857B2

公开(公告)日：2023-12-26

申请号：US16889853

申请日：2020-06-02

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Veeramanikandan Raju ,  Chaitanya Ghone ,  Deepak Poddar

IPC: G06N3/04 ,  G06N3/088 ,  H04L9/40 ,  G06N3/045

CPC classification number: G06N3/04 ,  G06N3/045 ,  G06N3/088 ,  H04L63/0435 ,  H04L63/0464

Abstract: A convolutional neural network (CNN)-based signal processing includes receiving of an encrypted output from a first layer of a multi-layer CNN data. The received encrypted output is subsequently decrypted to form a decrypted input to a second layer of the multi-layer CNN data. A convolution of the decrypted input with a corresponding decrypted weight may generate a second layer output, which may be encrypted and used as an encrypted input to a third layer of the multi-layer CNN data.

公开(公告)号：US11756169B2

公开(公告)日：2023-09-12

申请号：US17119714

申请日：2020-12-11

Applicant: Texas Instruments Incorporated

Inventor： Gang Hua ,  Rajasekhar Reddy Allu ,  Niraj Nandan ,  Mihir Narendra Mody

IPC: G06T5/00 ,  G06T7/60 ,  G06T11/40 ,  G06T3/00

CPC classification number: G06T5/006 ,  G06T3/0093 ,  G06T7/60 ,  G06T11/40 ,  G06T2207/20021

Abstract: A method for error handling in a geometric correction engine (GCE) is provided that includes receiving configuration parameters by the GCE, generating, by the GCE in accordance with the configuration parameters, output blocks of an output frame based on corresponding blocks of an input frame, detecting, by the GCE, a run-time error during the generating, and reporting, by the GCE, an event corresponding to the run-time error.

公开(公告)号：US11748599B2

公开(公告)日：2023-09-05

申请号：US16797871

申请日：2020-02-21

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Kumar Desappan ,  Mihir Narendra Mody ,  Pramod Kumar Swami ,  Anshu Jain ,  Rishabh Garg

IPC: G06F12/00 ,  G06N3/063 ,  G06T1/60 ,  G06F12/0804 ,  G06N3/08

CPC classification number: G06N3/063 ,  G06F12/0804 ,  G06N3/08 ,  G06T1/60

Abstract: Techniques including receiving a first set of values for processing by a machine learning (ML) network, storing a first portion of the first set of values in an on-chip memory, processing the first portion of the first set of values in a first layer of the ML network to generate a second portion of a second set of values, overwriting the stored first portion with the generated second portion, processing the second portion in a second layer of the ML network to generate a third portion of a third set of values, storing the third portion, repeating the steps of storing the first portion, processing the first portion, overwriting the stored first portion, processing the second portion, and storing the third portion for a fourth portion of the first set of values until all portions of the first set of values are processed to generate the third set of values.

公开(公告)号：US11736700B2

公开(公告)日：2023-08-22

申请号：US17543183

申请日：2021-12-06

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody

IPC: H04N19/174 ,  H04N19/436

CPC classification number: H04N19/174 ,  H04N19/436

Abstract: A video hardware engine with multi-threading functionality is disclosed. The video hardware engine includes a video hardware accelerator unit and a controller. The controller is coupled to the video hardware accelerator unit. The controller operates in an encode mode and a decode mode. In the encode mode, the controller receives a plurality of frames and encode attributes associated with each frame of the plurality of frames. The encode attributes associated with a frame of the plurality of frames is processed to generate encode parameters associated with the frame. The video hardware accelerator unit is configured to process the frame based on the encode parameters to generate an output. The output of the video hardware accelerator unit is processed to generate a compressed bit-stream and an encode status. In decode mode, the controller receives a compressed bit-stream and decode attributes and generates a plurality of frames and a decode status.

公开(公告)号：US20230259402A1

公开(公告)日：2023-08-17

申请号：US18302945

申请日：2023-04-19

Applicant: Texas Instruments Incorporated

Inventor： Niraj Nandan ,  Hetul Sanghvi ,  Mihir Narendra Mody

IPC: G06F9/50 ,  G06F9/48 ,  G06F11/07 ,  G06F9/52

CPC classification number: G06F9/5044 ,  G06F9/4887 ,  G06F11/0757 ,  G06F9/52

Abstract: Systems include data processors to process a set of image data in parallel, and thread schedulers coupled to the data processors. Each of the thread schedulers provides a respective task start signal for a respective data processor. Such systems also include a bandwidth controller coupled to one or more data processors. The bandwidth controller is configured to, for each of the data processor(s): maintain a respective token count, and determine whether to stall or propagate the respective task start signal from the respective thread scheduler to the data processor based on the respective token count. Other aspects include pattern adaptors respectively provided in the schedulers to allow mixing of multiple data patterns across blocks of data, transaction aggregators that allow re-using the same image data by multiple threads of execution while the image data remains in a given data buffer, and timers to detect failure and hang events.

公开(公告)号：US20230244557A1

公开(公告)日：2023-08-03

申请号：US18132683

申请日：2023-04-10

Applicant: Texas Instruments Incorporated

Inventor： Kedar Satish Chitnis ,  Charles Lance Fuoco ,  Sriramakrishnan Govindarajan ,  Mihir Narendra Mody ,  William A. Mills ,  Gregory Raymond Shurtz ,  Amritpal Singh Mundra

IPC: G06F9/54 ,  G06F9/50 ,  G06F9/38 ,  G06F9/455 ,  G06F9/48

CPC classification number: G06F9/546 ,  G06F9/5027 ,  G06F9/3836 ,  G06F9/45558 ,  G06F9/4806 ,  G06F2009/45583 ,  G06F2009/45587

Abstract: This disclosure relates to various implementations an embedded computing system. The embedded computing system comprises a hardware accelerator (HWA) thread user and a second HWA thread user that creates and sends out message requests. The HWA thread user and the second HWA thread user is communication with a microcontroller (MCU) subsystem. The embedded computing system also comprises a first inter-processor communication (IPC) interface between the HWA thread user and the MCU subsystem and a second IPC interface between the second HWA thread user and the MCU subsystem, where the first IPC interface is isolated from the second IPC interface. The MCU subsystem is also in communication with a first domain specific HWA and a second domain specific HWA.

公开(公告)号：US11710030B2

公开(公告)日：2023-07-25

申请号：US16556733

申请日：2019-08-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Mihir Narendra Mody ,  Prithvi Shankar Yeyyadi Anantha

IPC: G06N3/063 ,  G06N3/04 ,  G06F15/78 ,  G06F11/10 ,  G06F17/16 ,  G06N3/048

CPC classification number: G06N3/063 ,  G06F11/1004 ,  G06F15/7807 ,  G06F17/16 ,  G06N3/048

Abstract: A hardware neural network engine which uses checksums of the matrices used to perform the neural network computations. For fault correction, expected checksums are compared with checksums computed from the matrix developed from the matrix operation. The expected checksums are developed from the prior stage of the matrix operations or from the prior stage of the matrix operations combined with the input matrices to a matrix operation. This use of checksums allows reading of the matrices from memory, the dot product of the matrices and the accumulation of the matrices to be fault corrected without triplication of the matrix operation hardware and extensive use of error correcting codes. The nonlinear stage of the neural network computation is done using triplicated nonlinear computational logic. Fault detection is done in a similar manner, with fewer checksums needed and correction logic removed as compared to the fault correction operation.

公开(公告)号：US11653031B2

公开(公告)日：2023-05-16

申请号：US17093695

申请日：2020-11-10

Applicant: Texas Instruments Incorporated

Inventor： Ranga Ramanujam Srinivasan ,  Chaitanya Satish Ghone ,  Mihir Narendra Mody ,  Minhua Zhou

IPC: H04N19/895 ,  H04N19/172 ,  H04N19/107 ,  H04N19/39 ,  H04N19/65

CPC classification number: H04N19/895 ,  H04N19/107 ,  H04N19/172 ,  H04N19/39 ,  H04N19/65

Abstract: A method is provided that includes receiving pictures of a video sequence in a video encoder, and encoding the pictures to generate a compressed video bit stream that is transmitted to a video decoder in real-time, wherein encoding the pictures includes selecting a picture to be encoded as a delayed duplicate intra-predicted picture (DDI), wherein the picture would otherwise be encoded as an inter-predicted picture (P-picture), encoding the picture as an intra-predicted picture (I-picture) to generate the DDI, wherein the I-picture is reconstructed and stored for use as a reference picture for a decoder refresh picture, transmitting the DDI to the video decoder in non-real time, selecting a subsequent picture to be encoded as the decoder refresh picture, and encoding the subsequent picture in the compressed bit stream as the decoder refresh picture, wherein the subsequent P-picture is encoded as a P-picture predicted using the reference picture.

公开(公告)号：US11463664B2

公开(公告)日：2022-10-04

申请号：US16911579

申请日：2020-06-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shashank Dabral ,  Mihir Narendra Mody ,  Denis Beaudoin ,  Niraj Nandan ,  Gang Hua

IPC: H04N9/04 ,  G06T3/40 ,  G06T5/00

Abstract: A method of de-mosaicing pixel data from an image processor includes generating a pixel block that includes a plurality of image pixels. The method also includes determining a first image gradient between a first set of pixels of the pixel block and a second image gradient between a second set of pixels of the pixel block. The method also includes determining a first adaptive threshold value based on intensity of a third set of pixels of the pixel block. The pixels of the third set of pixels are adjacent to one another. The method also includes filtering the pixel block in a vertical, horizontal, or neutral direction based on the first and second image gradients and the first adaptive threshold value utilizing a plurality of FIR filters to generate a plurality of component images.

公开(公告)号：US11443505B2

公开(公告)日：2022-09-13

申请号：US16898972

申请日：2020-06-11

Applicant: Texas Instruments Incorporated

Inventor： Mihir Narendra Mody ,  Manu Mathew ,  Chaitanya Satish Ghone

IPC: G06V10/44 ,  G06K9/62 ,  G06V10/42

Abstract: A method for analyzing images to generate a plurality of output features includes receiving input features of the image and performing Fourier transforms on each input feature. Kernels having coefficients of a plurality of trained features are received and on-the-fly Fourier transforms (OTF-FTs) are performed on the coefficients in the kernels. The output of each Fourier transform and each OTF-FT are multiplied together to generate a plurality of products and each of the products are added to produce one sum for each output feature. Two-dimensional inverse Fourier transforms are performed on each sum.