公开(公告)号：US20210183794A1

公开(公告)日：2021-06-17

申请号：US16846416

申请日：2020-04-13

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tzu-Chun Tang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang ,  Chia-Chia Lin

IPC: H01L23/64 ,  H01L23/31 ,  H01L23/48 ,  H01L21/56 ,  H01L49/02

Abstract: Provided is a package structure including a first die; a plurality of through vias, aside the first die; a first encapsulant laterally encapsulating the first die and the plurality of through vias; a first redistribution layer (RDL) structure on first sides of the first die, plurality of through vias, and the first encapsulant; a second RDL structure on second sides of the first die, the plurality of through vias, and the first encapsulant; and a plurality of conductive connectors, electrically connected to the second RDL structure. Portions of the first RDL structure, the plurality of through vias, and the second RDL structure are electrically connected to each other and form a solenoid inductor laterally aside the first die.

公开(公告)号：US11011460B2

公开(公告)日：2021-05-18

申请号：US16858749

申请日：2020-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tin-Hao Kuo

IPC: H01L23/52 ,  H01L21/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L23/498

Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.

公开(公告)号：US10996410B2

公开(公告)日：2021-05-04

申请号：US16686224

申请日：2019-11-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Jeng-Shien Hsieh ,  Hsing-Kuo Hsia ,  Chen-Hua Yu

IPC: G02B6/12 ,  G02B6/42 ,  G02B6/122

Abstract: Semiconductor packages are provided. The semiconductor package includes a photonic integrated circuit, an electronic integrated circuit and a high performance integrated circuit. The electronic integrated circuit is disposed aside the photonic integrated circuit and electrically connected to the photonic integrated circuit through a first redistribution structure. The high performance integrated circuit is disposed aside the electronic integrated circuit and electrically connected to the electronic integrated circuit through a second redistribution structure.

公开(公告)号：US20210118858A1

公开(公告)日：2021-04-22

申请号：US16882054

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Chieh-Yen Chen

IPC: H01L25/16 ,  H01L23/00

Abstract: In an embodiment, a structure includes: a processor device including logic devices; a first memory device directly face-to-face bonded to the processor device by metal-to-metal bonds and by dielectric-to-dielectric bonds; a first dielectric layer laterally surrounding the first memory device; a redistribution structure over the first dielectric layer and the first memory device, the redistribution structure including metallization patterns; and first conductive vias extending through the first dielectric layer, the first conductive vias connecting the metallization patterns of the redistribution structure to the processor device.

公开(公告)号：US20210118759A1

公开(公告)日：2021-04-22

申请号：US16882132

申请日：2020-05-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chen-Hua Yu ,  Wei Ling Chang ,  Chuei-Tang Wang ,  Fong-yuan Chang ,  Chieh-Yen Chen

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/02

Abstract: In an embodiment, a device includes: a processor die including circuit blocks, the circuit blocks including active devices of a first technology node; a power gating die including power semiconductor devices of a second technology node, the second technology node larger than the first technology node; and a first redistribution structure including first metallization patterns, the first metallization patterns including power supply source lines and power supply ground lines, where a first subset of the circuit blocks is electrically coupled to the power supply source lines and the power supply ground lines through the power semiconductor devices, and a second subset of the circuit blocks is permanently electrically coupled to the power supply source lines and the power supply ground lines.

公开(公告)号：US20210096310A1

公开(公告)日：2021-04-01

申请号：US16882773

申请日：2020-05-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chih-Chieh Chang ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A package assembly and a manufacturing method thereof are provided. The package assembly includes a first package component and an optical signal port disposed aside the first package component. The first package component includes a first die including an electronic integrated circuit, a first insulating encapsulation laterally covering the first die, a redistribution structure disposed on the first die and the first insulating encapsulation, and a second die including a photonic integrated circuit and electrically coupled to the first die through the redistribution structure. The optical signal port is optically coupled to an edge facet of the second die of the first package component.

公开(公告)号：US20210074694A1

公开(公告)日：2021-03-11

申请号：US17099179

申请日：2020-11-16

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yu-Chih Huang ,  Chi-Hui Lai ,  Ban-Li Wu ,  Ying-Cheng Tseng ,  Ting-Ting Kuo ,  Chih-Hsuan Tai ,  Hao-Yi Tsai ,  Chuei-Tang Wang ,  Chung-Shi Liu ,  Chen-Hua Yu ,  Chiahung Liu

IPC: H01L25/16 ,  H01L23/498 ,  H01L21/48 ,  H01L21/50 ,  H01L23/31 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes an integrated passive device (IPD) including one or more passive devices over a first substrate; and metallization layers over and electrically coupled to the one or more passive devices, where a topmost metallization layer of the metallization layers includes a first plurality of conductive patterns; and a second plurality of conductive patterns interleaved with the first plurality of conductive patterns. The IPD also includes a first under bump metallization (UBM) structure over the topmost metallization layer, where the first UBM structure includes a first plurality of conductive strips, each of the first plurality of conductive strips electrically coupled to a respective one of the first plurality of conductive patterns; and a second plurality of conductive strips interleaved with the first plurality of conductive strips, each of the second plurality of conductive strips electrically coupled to a respective one of the second plurality of conductive patterns.

公开(公告)号：US10679947B2

公开(公告)日：2020-06-09

申请号：US15905722

申请日：2018-02-26

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Chen-Hua Yu

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L21/48 ,  H01L21/56 ,  H01L21/683 ,  H01L25/00

Abstract: A chip package includes a redistribution layer, at least one first semiconductor chip, an integrated fan-out package, and an insulating encapsulation. The at least one first semiconductor chip and the integrated fan-out package are electrically connected to the redistribution layer, wherein the at least one first semiconductor chip and the integrated fan-out package are located on a surface of the redistribution layer and electrically communicated to each other through the redistribution layer, and wherein the integrated fan-out package includes at least one second semiconductor chip. The insulating encapsulation encapsulates the at least one first semiconductor chip and the integrated fan-out package.

公开(公告)号：US20200091063A1

公开(公告)日：2020-03-19

申请号：US16134971

申请日：2018-09-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Ting Chen ,  Chung-Hao Tsai ,  Chen-Hua Yu ,  Chuei-Tang Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/48 ,  H01L25/16 ,  H01L23/00 ,  H01L21/56

Abstract: A semiconductor structure including at least one integrated circuit component is provided. The at least one integrated circuit component includes a first semiconductor substrate and a second semiconductor substrate electrically coupled to the first semiconductor substrate, wherein the first semiconductor substrate and the second semiconductor substrate are bonded through a first hybrid bonding interface, and at least one of the first semiconductor substrate or the second semiconductor substrate includes at least one first embedded capacitor.

公开(公告)号：US20190393149A1

公开(公告)日：2019-12-26

申请号：US16016664

申请日：2018-06-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chuei-Tang Wang ,  Tin-Hao Kuo

IPC: H01L23/522 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498

Abstract: A package structure including an interposer, a semiconductor die, through insulator vias, an insulating encapsulant and a redistribution layer is provided. The interposer includes a core structure having a first and second surface, first metal layers disposed on the first and second surface, second metal layers disposed on the second surface over the first metal layers, and third metal layers disposed on the second surface over the second metal layers. The semiconductor die is disposed on the interposer. The through insulator vias are disposed on the interposer and electrically connected to the plurality of first metal layers. The insulating encapsulant is disposed on the interposer over the first surface and encapsulating the semiconductor die and the plurality of through insulator vias. The redistribution layer is disposed on the insulating encapsulant and electrically connected to the semiconductor die and the plurality of through insulator vias.