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51.
公开(公告)号:US10347762B1
公开(公告)日:2019-07-09
申请号:US15991570
申请日:2018-05-29
Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
Inventor: Su-Hao Liu , Kuo-Ju Chen , Chun-Hung Wu , Chia-Cheng Chen , Liang-Yin Chen , Huicheng Chang , Ying-Lang Wang
IPC: H01L27/088 , H01L29/78 , H01L21/02 , H01L21/3115 , H01L29/66 , H01L21/8234 , H01L29/165 , H01L21/3215
Abstract: Embodiments disclosed herein relate generally to forming an ultra-shallow junction having high dopant concentration and low contact resistance in a p-type source/drain region. In an embodiment, a method includes forming a source/drain region in an active area on a substrate, the source/drain region comprising germanium, performing an ion implantation process using gallium (Ga) to form an amorphous region in the source/drain region, performing an ion implantation process using a dopant into the amorphous region, and subjecting the amorphous region to a thermal process.
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公开(公告)号:US09666302B1
公开(公告)日:2017-05-30
申请号:US14980390
申请日:2015-12-28
Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
Inventor: Ming-Hung Chang , Chia-Cheng Chen , Ching-Wei Wu
IPC: G01R31/28 , G11C29/38 , G11C29/44 , G11C11/419 , G11C11/418
CPC classification number: G11C7/10 , G11C7/1045 , G11C29/12 , G11C29/54 , G11C29/70
Abstract: An IC includes a memory core logic unit, an output unit, and an input unit. The memory logic unit is coupled to a plurality of bit cells configured to control read and write of data to and from the plurality of bit cells. The input unit is formed on the integrated circuit. The output unit is formed on the integrated circuit. The input unit includes a second plurality of multiplexers for signal selection, at least one lock up latch for storing data and configured to increase a hold time for the data, and at least one shadow latch configured to store a copy of the data stored in the at least one lock up latch. The output unit includes a first plurality of multiplexers for signal selection and at least one high phase pass latch for storing data.
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