中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

31 records (took 0.018 seconds)

    Semiconductor device and method of manufacture
    1.
    发明授权
    Semiconductor device and method of manufacture 有权

    公开(公告)号：US12300717B2

    公开(公告)日：2025-05-13

    申请号：US17670740

    申请日：2022-02-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/786

    Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

    Semiconductor device and method of manufacture
    2.
    发明授权
    Semiconductor device and method of manufacture 有权

    公开(公告)号：US12218196B2

    公开(公告)日：2025-02-04

    申请号：US17670924

    申请日：2022-02-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01L29/06 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: A method includes depositing a multi-layer stack on a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a dummy gate on the multi-layer stack; forming a first spacer on a sidewall of the dummy gate; performing a first implantation process to form a first doped region, the first implantation process having a first implant energy and a first implant dose; performing a second implantation process to form a second doped region, where the first doped region and the second doped region are in a portion of the channel layers uncovered by the first spacer and the dummy gate, the second implantation process having a second implant energy and a second implant dose, where the second implant energy is greater than the first implant energy, and where the first implant dose is different from the second implant dose.

    Methodology for pattern correction
    4.
    发明授权
    Methodology for pattern correction 有权
    模式校正方法

    公开(公告)号：US09026955B1

    公开(公告)日：2015-05-05

    申请号：US14051568

    申请日：2013-10-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50

    CPC classification number: G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

    Abstract translation: 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

    Methodology for pattern density optimization
    8.
    发明授权
    Methodology for pattern density optimization 有权

    公开(公告)号：US10049178B2

    公开(公告)日：2018-08-14

    申请号：US15170026

    申请日：2016-06-01

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

    IPC: G06F17/50 ,  G03F1/36

    Abstract: The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE
    10.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURE 有权

    公开(公告)号：US20230042196A1

    公开(公告)日：2023-02-09

    申请号：US17670740

    申请日：2022-02-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yu-Chang Lin ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

    IPC: H01L29/06 ,  H01L29/786 ,  H01L21/8234

    Abstract: A method includes depositing a multi-layer stack over a semiconductor substrate, the multi-layer stack including a plurality of sacrificial layers that alternate with a plurality of channel layers; forming a first recess in the multi-layer stack; forming first spacers on sidewalls of the sacrificial layers in the first recess; depositing a first semiconductor material in the first recess, where the first semiconductor material is undoped, where the first semiconductor material is in physical contact with a sidewall and a bottom surface of at least one of the first spacers; implanting dopants in the first semiconductor material, where after implanting dopants the first semiconductor material has a gradient-doped profile; and forming an epitaxial source/drain region in the first recess over the first semiconductor material, where a material of the epitaxial source/drain region is different from the first semiconductor material.

Patent Agency Ranking