公开(公告)号：US20230061485A1

公开(公告)日：2023-03-02

申请号：US17463000

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/768

摘要： A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US09026955B1

公开(公告)日：2015-05-05

申请号：US14051568

申请日：2013-10-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Feng-Ju Chang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC分类号： G06F17/50

CPC分类号： G03F1/36 ,  G03F7/70433 ,  H01L21/3212 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present disclosure relates to a method of integrated chip (IC) design pattern correction that reduces pattern correction cycle time by separately correcting main feature shapes and dummy shapes of the IC design, and an associated apparatus. In some embodiments, the method is performed by forming an IC design having a plurality of main feature shapes. A plurality of dummy shapes are added to the IC design to improve a process window of the IC design. The plurality of main feature shapes are corrected using a first pattern correction process. One or more of the plurality of dummy shapes are subsequently corrected using a second pattern correction process separate from the first pattern correction process. By separately correcting dummy shapes and main feature shapes, the dummy shapes can be subjected to a different pattern correction process having lower time/resource demands, thereby reducing the pattern correction cycle time.

摘要翻译： 本公开涉及通过分开校正IC设计的主要特征形状和虚拟形状以及相关联的装置来减少图案校正周期时间的集成芯片（IC）设计图案校正的方法。 在一些实施例中，通过形成具有多个主要特征形状的IC设计来执行该方法。 将多个虚拟形状添加到IC设计中以改善IC设计的处理窗口。 使用第一图案校正处理来校正多个主要特征形状。 随后使用与第一图案校正处理分开的第二图案校正处理来校正多个虚拟形状中的一个或多个。 通过单独地校正虚拟形状和主要特征形状，可以对虚拟形状进行具有较低时间/资源需求的不同的图案校正处理，从而减少图案校正周期时间。

公开(公告)号：US11776810B2

公开(公告)日：2023-10-03

申请号：US17463000

申请日：2021-08-31

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chia-Cheng Chen ,  Chun-Hung Wu ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo ,  Chun-Yen Chang ,  Chih-Kai Yang ,  Yu-Tien Shen ,  Ya Hui Chang

IPC分类号： H01L21/027 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L21/0274 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802

摘要： A method for forming a semiconductor device is provided. In some embodiments, the method includes forming a target layer over a semiconductor substrate, forming a carbon-rich hard masking layer over the target layer, patterning features in the carbon-rich hard masking layer using an etching process, performing a directional ion beam trimming process on the features patterned in the carbon-rich hard masking layer, and patterning the target layer using the carbon-rich hard masking layer as a mask.

公开(公告)号：US20220310785A1

公开(公告)日：2022-09-29

申请号：US17566316

申请日：2021-12-30

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hung Wu ,  Chia-Ling Chung ,  Su-Hao Liu ,  Liang-Yin Chen ,  Shun-Wu Lin ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L29/06 ,  H01L29/786 ,  H01L21/8234 ,  H01L21/425

摘要： A method of forming a semiconductor device including performing an ion implantation on a substrate and etching the substrate and semiconductor devices formed by the same are disclosed. In an embodiment, a method includes forming a transistor on a first side of a substrate; performing an ion implantation on a second side of the substrate opposite the first side; after performing the ion implantation, etching the substrate to remove the substrate and form a first recess; and forming a dielectric layer in the first recess.

公开(公告)号：US11450741B2

公开(公告)日：2022-09-20

申请号：US17201041

申请日：2021-03-15

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC分类号： H01L21/8234 ,  H01L29/08 ,  H01L29/167 ,  H01L29/78 ,  H01L21/02 ,  H01L21/285 ,  H01L29/66 ,  H01L21/265 ,  H01L29/417

摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US10049178B2

公开(公告)日：2018-08-14

申请号：US15170026

申请日：2016-06-01

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Hung-Chun Wang ,  Ming-Hui Chih ,  Ping-Chieh Wu ,  Chun-Hung Wu ,  Wen-Hao Liu ,  Cheng-Hsuan Huang ,  Cheng-Kun Tsai ,  Wen-Chun Huang ,  Ru-Gun Liu

IPC分类号： G06F17/50 ,  G03F1/36

摘要： The present disclosure relates to a method of improving pattern density with a low OPC (optical proximity correction) cycle time, and an associated apparatus. In some embodiments, the method is performed by performing an initial data preparation process on an IC design including a graphical representation of a layout used to fabricate an integrated chip. The initial data preparation process is performed by using a data preparation element to generate a modified IC design having modified shapes that are modified forms of shapes within the IC design. One or more low-pattern-density areas of the modified IC design are identified using a local density checking element. One or more dummy shapes are added within the one or more low-pattern-density areas using a dummy shape insertion element. The one or more dummy shapes are separated from the modified shapes by a non-zero space.

公开(公告)号：US12087578B2

公开(公告)日：2024-09-10

申请号：US17651851

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213

CPC分类号： H01L21/0273 ,  H01L21/31144 ,  H01L21/32139

摘要： A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.

公开(公告)号：US12015055B2

公开(公告)日：2024-06-18

申请号：US18350838

申请日：2023-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC分类号： H01L29/08 ,  H01L21/02 ,  H01L21/265 ,  H01L21/285 ,  H01L29/167 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20230352533A1

公开(公告)日：2023-11-02

申请号：US18350838

申请日：2023-07-12

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Su-Hao Liu ,  Huicheng Chang ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Kuo-Ju Chen ,  Chun-Hung Wu ,  Chang-Miao Liu ,  Huai-Tei Yang ,  Lun-Kuang Tan ,  Wei-Ming You

IPC分类号： H01L21/02 ,  H01L21/265 ,  H01L29/78 ,  H01L29/66 ,  H01L29/417 ,  H01L29/08 ,  H01L29/167 ,  H01L21/285

CPC分类号： H01L29/0847 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/26513 ,  H01L21/28518 ,  H01L29/167 ,  H01L29/41791 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785

摘要： The present disclosure relates generally to doping for conductive features in a semiconductor device. In an example, a structure includes an active region of a transistor. The active region includes a source/drain region, and the source/drain region is defined at least in part by a first dopant having a first dopant concentration. The source/drain region further includes a second dopant with a concentration profile having a consistent concentration from a surface of the source/drain region into a depth of the source/drain region. The consistent concentration is greater than the first dopant concentration. The structure further includes a conductive feature contacting the source/drain region at the surface of the source/drain region.

公开(公告)号：US20220406592A1

公开(公告)日：2022-12-22

申请号：US17651851

申请日：2022-02-21

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chun-Hung Wu ,  Chia-Cheng Chen ,  Liang-Yin Chen ,  Huicheng Chang ,  Yee-Chia Yeo

IPC分类号： H01L21/027 ,  H01L21/311 ,  H01L21/3213

摘要： A method of forming a semiconductor device includes forming a photoresist over a target layer, where the target layer includes a substrate. The photoresist is patterned to form a patterned photoresist. Scum remains between portions of the patterned photoresist. The substrate is tilted relative to a direction of propagation of an ion beam. An ion treatment is performed on the scum. A pattern of the patterned photoresist is transferred to the target layer.