公开(公告)号：US20220028684A1

公开(公告)日：2022-01-27

申请号：US17156365

申请日：2021-01-22

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Yen-Yu CHEN ,  Chib-Cheng LIU ,  Yi-Ohen KUO ,  Jr-Hung Li ,  Tze-Liang LEE ,  Ming-Hui WENG ,  Yahru CHENG

IPC: H01L21/027 ,  H01L21/311 ,  H01L21/308

Abstract: A method of manufacturing a semiconductor device includes forming a photoresist layer over a substrate and forming a dehydrated film over the photoresist layer. The photoresist layer is selectively exposed to actinic radiation to form an exposed portion and an unexposed portion of the photoresist layer. The photoresist layer is developed to remove the unexposed portion of the photoresist layer and a first portion of the dehydrated film over the unexposed portion of the photoresist layer. In an embodiment, the method includes etching the substrate by using the exposed portion of the photoresist layer as a mask.

公开(公告)号：US20210098584A1

公开(公告)日：2021-04-01

申请号：US16805862

申请日：2020-03-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Hsien Cheng ,  Jr-Hung Li ,  Tai-Chun Huang ,  Tze-Liang Lee ,  Chung-Ting Ko ,  Jr-Yu Chen ,  Wan-Chen Hsieh

IPC: H01L29/417 ,  H01L29/78 ,  H01L29/08 ,  H01L29/66

Abstract: A semiconductor device includes a substrate, a gate structure on the substrate, a source/drain (S/D) region and a contact. The S/D region is located in the substrate and on a side of the gate structure. The contact lands on and connected to the S/D region. The contact wraps around the S/D region.

公开(公告)号：US20200075419A1

公开(公告)日：2020-03-05

申请号：US16674443

申请日：2019-11-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Bo-Cyuan Lu ,  Chunyao Wang ,  Jr-Hung Li ,  Chung-Ting Ko ,  Chi On Chui

IPC: H01L21/8234 ,  H01L29/66 ,  H01L27/088 ,  H01L29/423 ,  H01L29/417 ,  H01L29/78

Abstract: Gate structures and gate spacers, along with methods of forming such, are described. In an embodiment, a structure includes an active area on a substrate, a gate structure on the active area and over the substrate, and a low-k gate spacer on the active area and along a sidewall of the gate structure. The gate structure includes a conformal gate dielectric on the active area and includes a gate electrode over the conformal gate dielectric. The conformal gate dielectric extends vertically along a first sidewall of the low-k gate spacer. In some embodiments, the low-k gate spacer can be formed using a selective deposition process after a dummy gate structure has been removed in a replacement gate process.