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    Packaged semiconductor devices including backside power rails and methods of forming the same
    51.
    发明授权
    Packaged semiconductor devices including backside power rails and methods of forming the same 有权

    公开(公告)号：US11239208B2

    公开(公告)日：2022-02-01

    申请号：US16994223

    申请日：2020-08-14

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Chi-Yi Chuang ,  Hou-Yu Chen ,  Kuan-Lun Cheng

    IPC: H01L23/00 ,  H01L23/528 ,  H01L25/00 ,  H01L25/065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/45 ,  H01L29/786

    Abstract: Methods for forming packaged semiconductor devices including backside power rails and packaged semiconductor devices formed by the same are disclosed. In an embodiment, a device includes a first integrated circuit device including a first transistor structure in a first device layer; a front-side interconnect structure on a front-side of the first device layer; and a backside interconnect structure on a backside of the first device layer, the backside interconnect structure including a first dielectric layer on the backside of the first device layer; and a first contact extending through the first dielectric layer to a source/drain region of the first transistor structure; and a second integrated circuit device including a second transistor structure in a second device layer; and a first interconnect structure on the second device layer, the first interconnect structure being bonded to the front-side interconnect structure by dielectric-to-dielectric and metal-to-metal bonds.

    Self-Aligned Metal Gate for Multigate Device
    56.
    发明申请
    Self-Aligned Metal Gate for Multigate Device 有权

    公开(公告)号：US20210343600A1

    公开(公告)日：2021-11-04

    申请号：US17174109

    申请日：2021-02-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Guan-Lin Chen ,  Kuo-Cheng Chiang ,  Chih-Hao Wang ,  Kuan-Lun Cheng ,  Ching-Wei Tsai ,  Shi Ning Ju ,  Jui-Chien Huang

    IPC: H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L21/28 ,  H01L29/66

    Abstract: Self-aligned gate cutting techniques for multigate devices are disclosed herein that provide multigate devices having asymmetric metal gate profiles and asymmetric source/drain feature profiles. An exemplary multigate device has a channel layer, a metal gate that wraps a portion of the channel layer, and source/drain features disposed over a substrate. The channel layer extends along a first direction between the source/drain features. A first dielectric fin and a second dielectric fin are disposed over the substrate and configured differently. The channel layer extends along a second direction between the first dielectric fin and the second dielectric fin. The metal gate is disposed between the channel layer and the second dielectric fin. In some embodiments, the first dielectric fin is disposed on a first isolation feature, and the second dielectric fin is disposed on a second isolation feature. The first isolation feature and the second isolation feature are configured differently.

    Selective Liner on Backside Via and Method Thereof
    57.
    发明申请
    Selective Liner on Backside Via and Method Thereof 有权

    公开(公告)号：US20210336004A1

    公开(公告)日：2021-10-28

    申请号：US16944263

    申请日：2020-07-31

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Lin-Yu Huang ,  Li-Zhen Yu ,  Chia-Hao Chang ,  Cheng-Chi Chuang ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L29/08 ,  H01L29/06 ,  H01L29/78

    Abstract: A method includes providing a structure having a substrate, a fin, source/drain (S/D) features, an isolation structure adjacent to sidewalls of the fin, one or more channel layers over a first dielectric layer and connecting the S/D features, and a gate structure engaging the one or more channel layers. The method further includes thinning down the structure from its backside until the fin is exposed and selectively etching the fin to form a trench that exposes surfaces of the S/D features, the first dielectric layer, and the isolation structure. The method further includes forming a silicide feature on the S/D features and depositing an inhibitor on the silicide feature but not on the surface of the first dielectric layer and the isolation structure, depositing a dielectric liner layer on the surfaces of the isolation structure and the first dielectric layer but not on the inhibitor, and selectively removing the inhibitor.

    Semiconductor Device and Method
    59.
    发明申请
    Semiconductor Device and Method 有权

    公开(公告)号：US20210313235A1

    公开(公告)日：2021-10-07

    申请号：US17340660

    申请日：2021-06-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Yi-Bo Liao ,  Kai-Chieh Yang ,  Ching-Wei Tsai ,  Kuan-Lun Cheng

    IPC: H01L21/8238 ,  H01L29/06 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3065 ,  H01L27/092

    Abstract: In an embodiment, a method includes: forming a first recess and a second recess in a substrate; growing a first epitaxial material stack in the first recess, the first epitaxial material stack including alternating layers of a first semiconductor material and a second semiconductor material, the layers of the first epitaxial material stack being undoped; growing a second epitaxial material stack in the second recess, the second epitaxial material stack including alternating layers of the first semiconductor material and the second semiconductor material, a first subset of the second epitaxial material stack being undoped, a second subset of the second epitaxial material stack being doped; patterning the first epitaxial material stack and the second epitaxial material stack to respectively form first nanowires and second nanowires; and forming a first gate structure around the first nanowires and a second gate structure around the second nanowires.

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