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    Gate Isolation for Multigate Device
    51.
    发明申请
    Gate Isolation for Multigate Device 有权

    公开(公告)号：US20210375858A1

    公开(公告)日：2021-12-02

    申请号：US17199777

    申请日：2021-03-12

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Chiang ,  Shi Ning Ju ,  Guan-Lin Chen ,  Kuan-Ting Pan ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L29/423 ,  H01L29/786 ,  H01L21/762

    Abstract: Gate cutting techniques disclosed herein form gate isolation fins to isolate metal gates of multigate devices from one another before forming the multigate devices, and in particular, before forming the metal gates of the multigate devices. An exemplary device includes a first multigate device having first source/drain features and a first metal gate that surrounds a first channel layer and a second multigate device having second source/drain features and a second metal gate that surrounds a second channel layer. A gate isolation fin, which separates the first metal gate and the second metal gate, includes a first dielectric layer having a first dielectric constant and a second dielectric layer having a second dielectric constant disposed over the first dielectric layer. The second dielectric constant is less than the first dielectric constant. A gate isolation end cap may be disposed on the gate isolation fin to provide additional isolation.

    Method for forming semiconductor device structure
    52.
    发明授权
    Method for forming semiconductor device structure 有权

    公开(公告)号：US10985277B2

    公开(公告)日：2021-04-20

    申请号：US16859779

    申请日：2020-04-27

    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kuo-Cheng Ching ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L29/78 ,  H01L29/66 ,  H01L27/088 ,  H01L29/16 ,  H01L21/8234

    Abstract: A method includes forming a first semiconductor layer over a substrate. A second semiconductor layer is formed over the first semiconductor layer. The first semiconductor layer and the second semiconductor layer are etched to form a fin structure that extends from the substrate. The fin structure has a remaining portion of first semiconductor layer and a remaining portion of the second semiconductor layer atop the remaining portion of the first semiconductor layer. A capping layer is formed to wrap around three sides of the fin structure. At least a portion of the capping layer and at least a portion of the remaining portion of the second semiconductor layer in the fin structure are oxidized to form an oxide layer wrapping around three sides of the fin structure.

    ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES
    56.
    发明申请
    ETCH PROFILE CONTROL OF POLYSILICON STRUCTURES OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20190164840A1

    公开(公告)日：2019-05-30

    申请号：US16246209

    申请日：2019-01-11

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Chih-Hao Wang ,  Kuan-Ting Pan

    IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/08 ,  H01L29/66 ,  H01L29/423 ,  H01L29/78

    Abstract: A method of forming first and second fin field effect transistors (finFETs) on a substrate includes forming first and second fin structures of the first and second finFETs, respectively, on the substrate and forming first and second oxide regions having first and second thicknesses on top surfaces of the first and second fin structures, respectively. The method further includes forming third and fourth oxide regions having third and fourth thicknesses on sidewalls on the first and second fin structures, respectively. The first and second thicknesses are greater than the third and fourth thicknesses, respectively. The method further includes forming a first polysilicon structure on the first and third oxide regions and forming a second polysilicon structure on the second and fourth oxide regions. The method also includes forming first and second source/drain regions on first and second recessed portions of the first and second fin structures, respectively and replacing the first and second polysilicon structures with first and second gate structures, respectively

    Buried Interconnect Conductor
    57.
    发明申请
    Buried Interconnect Conductor 审中-公开

    公开(公告)号：US20190035785A1

    公开(公告)日：2019-01-31

    申请号：US15698030

    申请日：2017-09-07

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuo-Cheng Ching ,  Shi Ning Ju ,  Kuan-Ting Pan ,  Kuan-Lun Cheng ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/308 ,  H01L21/762 ,  H01L29/66

    Abstract: Various examples of a buried interconnect line are disclosed herein. In an example, a device includes a fin disposed on a substrate. The fin includes an active device. A plurality of isolation features are disposed on the substrate and below the active device. An interconnect is disposed on the substrate and between the plurality of isolation features such that the interconnect is below a topmost surface of the plurality of isolation features. The interconnect is electrically coupled to the active device. In some such examples, a gate stack of the active device is disposed over a channel region of the active device and is electrically coupled to the interconnect. In some such examples, a source/drain contact is electrically coupled to a source/drain region of the active device, and the source/drain contact is electrically coupled to the interconnect.

    FINFET PITCH SCALING
    59.
    发明公开
    FINFET PITCH SCALING 审中-公开

    公开(公告)号：US20240363629A1

    公开(公告)日：2024-10-31

    申请号：US18768881

    申请日：2024-07-10

    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

    Inventor： Kuan-Ting Pan ,  Yi-Ruei Jhan ,  Kuo-Cheng Chiang ,  Chih-Hao Wang

    IPC: H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L29/78

    CPC classification number: H01L27/0886 ,  H01L21/823431 ,  H01L21/823468 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

    Abstract: According to one example, a semiconductor structure includes a fin-shaped structure, a gate structure disposed over a region of the fin-shaped structure and having a sidewall including a lower portion and an upper portion above the lower portion, a first dielectric sidewall structure disposed along the lower portion of the sidewall, a second dielectric sidewall structure disposed along the upper portion of the sidewall and disposed on the first dielectric sidewall structure, and a source/drain feature disposed over a source/drain region of the fin-shaped structure and adjacent to the gate structure. The source/drain feature is separated from the gate structure by the first dielectric sidewall structure and the second dielectric sidewall structure. The first dielectric sidewall structure includes a different material than the second dielectric sidewall structure.

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