公开(公告)号：US06214680B1

公开(公告)日：2001-04-10

申请号：US09460111

申请日：1999-12-13

Applicant: Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

Inventor： Shyue Fong Quek ,  Ting Cheong Ang ,  Puay Ink Ong ,  Sang Yee Loong

IPC: H01L21336

CPC classification number: H01L29/66492 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

Abstract: A new method of fabricating a MOSFET device is described. A semiconductor substrate is provided and isolation areas are formed isolating active areas in the substrate. An oxide layer is provided overlying both the substrate and isolation area and is patterned and etched to expose two areas within an isolated active area of the substrate. Selective epitaxial growth (SEG) using intrinsic silicon is performed to fill the exposed substrate areas formed in the previous etch step. The oxide layer region in the active area between the two epitaxially grown silicon regions is then etched, exposing the substrate. This is followed by a gate oxide growth and a polysilicon deposition. Planarization is then performed on the surface to expose the two epitaxially grown silicon regions. A second oxide is grown consuming some of the polysilicon gate and the epitaxially grown silicon. This consumption occurs at a higher rate at the upper surface and thus shapes the gate and epitaxially grown silicon into trapezoids with the base being wider than the top. The oxide is then etched leaving V-shaped trenches between the polysilicon and epitaxially grown silicon. A low-angle implantation is performed creating the source/drain extensions in the substrate below the V-shaped trenches. A third oxide is deposited filling the V-shaped groove and overlying the surface of the wafer. A second planarization is performed exposing the top of the epitaxially grown silicon regions and the polysilicon gate. A second implantation is performed to dope the polysilicon gate and epitaxially grown silicon regions. The doped portions of the epitaxially grown silicon form the source drain electrodes of the MOSFET. This is then followed by a salicidation step for metalization and annealing of the second implantation completing the MOSFET device.

Abstract translation: 描述了一种制造MOSFET器件的新方法。 提供半导体衬底，并且形成隔离区域以隔离衬底中的有源区域。 提供覆盖衬底和隔离区域的氧化物层，并且被图案化和蚀刻以暴露衬底的隔离有效区域内的两个区域。 执行使用本征硅的选择性外延生长（SEG）以填充在先前蚀刻步骤中形成的暴露的衬底区域。 然后蚀刻两个外延生长的硅区域之间的有源区域中的氧化物层区域，暴露衬底。 之后是栅极氧化物生长和多晶硅沉积。 然后在表面上进行平面化以暴露两个外延生长的硅区域。 第二氧化物生长消耗一些多晶硅栅极和外延生长的硅。 这种消耗以较高的速率发生在上表面，因此将浇口和外延生长的硅形成为梯形，基部比顶部宽。 然后蚀刻氧化物，留下多晶硅和外延生长的硅之间的V形沟槽。 执行低角度注入，在V形沟槽下面的衬底中产生源极/漏极延伸部。 沉积填充V形槽并覆盖晶片表面的第三氧化物。 进行外延生长的硅区域和多晶硅栅极的顶部的第二平面化。 进行第二次注入以掺杂多晶硅栅极和外延生长的硅区域。 外延生长硅的掺杂部分形成MOSFET的源极漏极。 然后进行用于金属化和退火完成MOSFET器件的第二次注入的盐析步骤。

公开(公告)号：US6143598A

公开(公告)日：2000-11-07

申请号：US246893

申请日：1999-02-08

Applicant: John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

Inventor： John Elmslie Martin ,  Lap Chan ,  John Leonard Sudijono ,  Ting Cheong Ang

IPC: H01L21/02 ,  H01L21/314 ,  H01L21/316 ,  H01L21/8242

CPC classification number: H01L28/40 ,  H01L28/60 ,  H01L21/3144 ,  H01L21/31604 ,  H01L27/10852

Abstract: A capacitor element of a semiconductor device used for high density semiconductor circuits is formed by the steps of forming the bottom plate of the capacitor, submitting the top of the bottom plate to plasma treatment in an oxidizing medium where nitrogen and oxygen are present, depositing a dielectric layer and submitting the top of the dielectric layer to plasma treatment in an oxidizing medium where nitrogen and oxygen are present. Various materials are used for the plasma treatment in an oxidizing medium where nitrogen and oxygen are present. While the present invention uses amorphous silicon as the dielectric material, plasma treatment in an oxidizing medium where nitrogen and oxygen are present can readily applied to a number of other dielectric materials. The objective in constructing capacitors for semiconductor circuits is to reduce the thickness of the dielectric material as much as possible and use a dielectric material for the dielectric which has a high dielectric constant, this increases the value of the capacitor electrical charge which can be carried by the capacitor. The objective of the present invention is to eliminate the leakage current between the plates of a capacitor so that the capacitor can maintain a high voltage between the top and the bottom plate.

Abstract translation: 用于高密度半导体电路的半导体器件的电容器元件是通过形成电容器的底板的步骤形成的，将底板的顶部在存在氮和氧的氧化介质中进行等离子体处理， 介电层，并将介电层的顶部在存在氮和氧的氧化介质中进行等离子体处理。 在存在氮和氧的氧化介质中使用各种材料进行等离子体处理。 虽然本发明使用非晶硅作为介电材料，但在存在氮和氧的氧化介质中的等离子体处理可以容易地应用于许多其它电介质材料。 用于半导体电路构造电容器的目的是尽可能地减小电介质材料的厚度，并且使用具有高介电常数的电介质的介电材料，这增加了电容器电荷的值 电容器。 本发明的目的是消除电容器板之间的漏电流，使得电容器能够在顶板和底板之间保持高电压。

公开(公告)号：US06090691A

公开(公告)日：2000-07-18

申请号：US439366

申请日：1999-11-15

Applicant: Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

Inventor： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

IPC: H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

CPC classification number: H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

Abstract: A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

Abstract translation: 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。