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    Method for forming a raised source and drain without using selective epitaxial growth
    1.
    发明授权
    Method for forming a raised source and drain without using selective epitaxial growth 有权
    在不使用选择性外延生长的情况下形成升高的源极和漏极的方法

    公开(公告)号：US06090691A

    公开(公告)日：2000-07-18

    申请号：US439366

    申请日：1999-11-15

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Xing Yu ,  Ying Keung Leung

    IPC分类号： H01L21/225 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/417 ,  H01L21/22

    CPC分类号： H01L29/66492 ,  H01L21/823814 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L21/2255 ,  H01L29/665

    摘要： A method for forming a raised source and drain structure without using selective epitaxial silicon growth. A semiconductor substrate is provided having one or more gate areas covered by dielectric structures. Doped polysilicon structures are adjacent to the dielectric structures on each side and are co-planar with the dielectric structures from a CMP process. The first dielectric structures are removed to form gate openings and a liner oxide layer is formed on the bottom and sidewalls of the gate openings. Dielectric spacers are formed on the liner oxide layer over the sidewalls of the gate openings, and the liner oxide layer is removed from the bottom of the gate openings and from over the doped polysilicon structures. Source and drain regions are formed in the semiconductor substrate by diffusing impurity ions from the doped polysilicon layer. A gate oxide layer and a gate polysilicon layer are formed over the semiconductor structure and the gate polysilicon layer is planarized to form a gate electrode. In a key step, the dielectric spacers are removed to form spacer openings, and impurity ions are implanted through the spacer openings and annealed to form source and drain extensions. The dielectric spacers are reformed and a self-aligned silicide layer is formed on the doped polysilicon structure and the gate electrode. Alternatively, the self-aligned silicide layer can be formed prior to removing the dielectric spacers and implanting ions to form source and drain extensions.

    摘要翻译： 一种用于在不使用选择性外延硅生长的情况下形成隆起的源极和漏极结构的方法。 提供具有被介电结构覆盖的一个或多个栅极区域的半导体衬底。 掺杂的多晶硅结构与每一侧上的电介质结构相邻，并且与来自CMP工艺的电介质结构共面。 去除第一电介质结构以形成栅极开口，并且在栅极开口的底部和侧壁上形成衬里氧化物层。 在栅极开口的侧壁上的衬垫氧化物层上形成介质间隔物，并且从栅极开口的底部和掺杂的多晶硅结构上方移除衬里氧化物层。 通过从掺杂多晶硅层扩散杂质离子，在半导体衬底中形成源区和漏区。 在半导体结构上形成栅极氧化物层和栅极多晶硅层，并且平坦化栅极多晶硅层以形成栅电极。 在关键步骤中，去除电介质间隔物以形成间隔开口，并通过间隔开孔注入杂质离子并退火以形成源极和漏极延伸部分。 电介质间隔物被重整，并且在掺杂多晶硅结构和栅电极上形成自对准的硅化物层。 或者，可以在去除电介质间隔物和注入离子以形成源极和漏极延伸部之前形成自对准硅化物层。

    Process to fabricate a source-drain extension
    3.
    发明授权
    Process to fabricate a source-drain extension 失效
    制造源极 - 漏极扩展的过程

    公开(公告)号：US06376319B2

    公开(公告)日：2002-04-23

    申请号：US09972629

    申请日：2001-10-09

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

    摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers
    4.
    发明授权
    Method for forming MOSFET device having source/drain extension regions located underlying L shaped spacers 有权
    用于形成具有位于L形间隔物下方的源极/漏极延伸区域的MOSFET器件的方法

    公开(公告)号：US06455384B2

    公开(公告)日：2002-09-24

    申请号：US09972645

    申请日：2001-10-09

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Jun Song ,  Xing Yu

    IPC分类号： H01L21336

    CPC分类号： H01L29/6653 ,  H01L29/66545 ,  H01L29/66553 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/7834

    摘要： A process for fabricating a MOSFET device, featuring source/drain extension regions, formed after the utilization of high temperature processes, such as heavily doped source/drain regions, has been developed. Disposable insulator spacers are formed on the sides of doped, SEG silicon regions, followed formation of a gate insulator layer, and an overlying gate structure, on a region of the semiconductor substrate located between the doped SEG silicon regions. The temperature experienced during these process steps result in the formation of the heavily doped source/drain, underlying the SEG silicon regions. Selective removal of the disposable spacers, allows the source/drain extension regions to be placed in the space vacated by the disposable spacers, adjacent to the heavily doped source/drain region. Insulator spacers are then used to fill the spaces vacated by removal of the disposable spacers, directly overlying the source/drain extension regions. Additional iterations include the use of an L shaped spacer, overlying the source/drain extension region, as well as the formation of metal silicide, on the doped SEG silicon regions, and on the gate structures.

    摘要翻译： 已经开发了一种用于制造MOSFET器件的方法，其特征在于在利用高温工艺（例如重掺杂源极/漏极区域）之后形成的源极/漏极延伸区域。 在掺杂的SEG硅区域的侧面上形成一次性绝缘体间隔物，随后在位于掺杂的SEG硅区域之间的半导体衬底的区域上形成栅极绝缘体层和覆盖栅极结构。 在这些工艺步骤中经历的温度导致SEG硅区域下方的重掺杂源极/漏极的形成。 选择性地去除一次性间隔件允许源极/漏极延伸区域被放置在与重掺杂的源极/漏极区域相邻的由一次性间隔物空出的空间中。 然后使用绝缘体间隔物来填充通过去除一次性间隔件而空出的空间，直接覆盖源极/漏极延伸区域。 另外的迭代包括在掺杂的SEG硅区域上以及栅极结构上使用覆盖源极/漏极延伸区域的L形间隔物以及金属硅化物的形成。

    Method of fabrication of a raised source/drain transistor
    5.
    发明授权
    Method of fabrication of a raised source/drain transistor 有权
    凸起源极/漏极晶体管的制造方法

    公开(公告)号：US6100161A

    公开(公告)日：2000-08-08

    申请号：US442494

    申请日：1999-11-18

    申请人： Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    发明人： Xing Yu ,  Ying Keung Leung ,  Hong Yang ,  Shyue Fong Quek

    IPC分类号： H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L21/76 ,  H01L21/4763

    CPC分类号： H01L29/66606 ,  H01L21/28518 ,  H01L21/823418 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545

    摘要： A method of fabricating a transistor, comprising the following steps. A silicon semiconductor substrate having a pad oxide portion within an active area is provided. A polysilicon layer is deposited over the silicon semiconductor substrate and over the pad oxide portion. A pad oxide layer is deposited over the polysilicon layer. Shallow isolation trench regions are formed on either side of the active area. The pad oxide layer is removed. The polysilicon layer is etched and removed over the pad oxide portion leaving polysilicon portions between the pad oxide portion and the shallow isolation trench regions. The pad oxide portion is replaced with a gate oxide portion. A gate conductor, having exposed side walls, is formed over the gate oxide portion and between the polysilicon portions. Sidewall spacers are formed on the exposed side walls of the gate conductor with the sidewall spacers contacting the polysilicon portions. Source/drain regions are formed in the active area under the sidewall spacers and under the polysilicon portions. A salicide portion is formed over the gate conductor and salicide portions are formed over the polysilicon portions, whereby the formation of the salicide layers over the polysilicon portions consumes a portion of the polysilicon portions leaving the remainder of the polysilicon layers to form shallow source/drain junctions underneath the polysilicon portion salicide portions.

    摘要翻译： 一种制造晶体管的方法，包括以下步骤。 提供了在有源区内具有衬垫氧化物部分的硅半导体衬底。 多晶硅层沉积在硅半导体衬底上并在衬垫氧化物部分上方。 在多晶硅层上沉积焊盘氧化物层。 在有源区域的两侧形成浅的隔离沟槽区域。 去除衬垫氧化物层。 在衬垫氧化物部分上蚀刻并除去多晶硅层，留下衬垫氧化物部分和浅隔离沟槽区域之间的多晶硅部分。 焊盘氧化物部分被栅氧化物部分代替。 具有暴露的侧壁的栅极导体形成在栅极氧化物部分上方和多晶硅部分之间。 侧壁间隔件形成在栅极导体的暴露的侧壁上，其中侧壁间隔件与多晶硅部分接触。 源极/漏极区域形成在侧壁间隔下方的有源区域和多晶硅部分下方。 在栅极导体上形成自对准硅化物部分，并且在多晶硅部分上形成自对准硅化物部分，由此在多晶硅部分上形成硅化物层消耗部分多晶硅部分留下剩余的多晶硅层以形成浅的源极/漏极 在多晶硅部分自对准硅化物部分下方的结。

    Vertical source/drain contact semiconductor
    7.
    发明授权
    Vertical source/drain contact semiconductor 有权
    垂直源极/漏极接触半导体

    公开(公告)号：US06465296B1

    公开(公告)日：2002-10-15

    申请号：US10167095

    申请日：2002-06-10

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Sang Yee Loong ,  Puay Ing Ong

    IPC分类号： H01L218238

    CPC分类号： H01L29/66772 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/41733 ,  H01L29/458 ,  H01L29/66636 ,  H01L29/66825 ,  H01L29/78621

    摘要： A semiconductor device and manufacturing process therefor is provided in which angled dopant implantation is followed by the formation of vertical trenches in the silicon on insulator substrate adjacent to the sides of the semiconductor gate. A second dopant implantation in the exposed the source/drain junctions is followed by a rapid thermal anneal that forms the semiconductor channel in the substrate. Contacts having inwardly curved cross-sectional widths in the semiconductor substrate are then formed which connect vertically to the exposed source/drain junctions either directly or through salicided contact areas.

    摘要翻译： 提供了一种半导体器件及其制造方法，其中倾斜的掺杂剂注入之后是在与半导体栅极的侧面相邻的绝缘体上硅衬底中形成垂直沟槽。 暴露在源极/漏极结中的第二掺杂剂注入之后是在衬底中形成半导体沟道的快速热退火。 然后形成在半导体衬底中具有向内弯曲的横截面宽度的触头，其直接地或通过咸水接触区域垂直连接到暴露的源极/漏极接合点。

    Triple-layered low dielectric constant dielectric dual damascene approach
    8.
    发明授权
    Triple-layered low dielectric constant dielectric dual damascene approach 有权
    三层低介电常数电介质双镶嵌方法

    公开(公告)号：US06406994B1

    公开(公告)日：2002-06-18

    申请号：US09726657

    申请日：2000-11-30

    申请人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

    发明人： Ting Cheong Ang ,  Shyue Fong Quek ,  Yee Chong Wong ,  Sang Yee Loong

    IPC分类号： H01L2144

    CPC分类号： B41M5/5254 ,  B41M5/508 ,  B41M5/5218 ,  B41M5/5272 ,  Y10T428/24802

    摘要： A triple layered low dielectric constant material dual damascene metallization process is described. Metal lines are provided covered by an insulating layer overlying a semiconductor substrate. A first dielectric layer of a first type is deposited overlying the insulating layer. A second dielectric layer of a second type is deposited overlying the first dielectric layer. A via pattern is etched into the second dielectric layer. Thereafter, a third dielectric layer of the first type is deposited overlying the patterned second dielectric layer. Simultaneously, a trench pattern is etched into the third dielectric layer and the via pattern is etched into the first dielectric layer to complete the formation of dual damascene openings in the fabrication of an integrated circuit device. If the first type is a low dielectric constant organic material, the second type will be a low dielectric constant inorganic material. If the first type is a low dielectric constant inorganic material, the second type will be a low dielectric constant organic material.

    摘要翻译： 描述了三层低介电常数材料双镶嵌金属化工艺。 金属线被覆盖在半导体衬底上的绝缘层所覆盖。 第一类型的第一介电层沉积在绝缘层上。 第二类型的第二介电层沉积在第一介电层上。 通孔图案被蚀刻到第二介电层中。 此后，第一类型的第三电介质层沉积在图案化的第二介电层上。 同时，沟槽图案被蚀刻到第三介电层中，并且通孔图案被蚀刻到第一介电层中，以在集成电路器件的制造中完成双镶嵌开口的形成。 如果第一种类型是低介电常数有机材料，则第二种类型将是低介电常数无机材料。 如果第一种类型是低介电常数无机材料，则第二类型将是低介电常数有机材料。

    Method of body contact for SOI MOSFET
    9.
    发明授权
    Method of body contact for SOI MOSFET 有权
    SOI MOSFET的体接触方法

    公开(公告)号：US06963113B2

    公开(公告)日：2005-11-08

    申请号：US10915670

    申请日：2004-08-10

    申请人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    发明人： Ting Cheong Ang ,  Sang Yee Loong ,  Shyue Fong Quek ,  Jun Song

    IPC分类号： H01L21/336 ,  H01L29/786 ,  H01L29/76

    CPC分类号： H01L29/66772 ,  H01L29/78615

    摘要： A new method for forming a silicon-on-insulator MOSFET while eliminating floating body effects is described. A silicon-on-insulator substrate is provided comprising a silicon semiconductor substrate underlying an oxide layer underlying a silicon layer. A first trench is etched partially through the silicon layer and not to the underlying oxide layer. Second trenches are etched fully through the silicon layer to the underlying oxide layer wherein the second trenches separate active areas of the semiconductor substrate and wherein one of the first trenches lies within each of the active areas. The first and second trenches are filled with an insulating layer. Gate electrodes and associated source and drain regions are formed in and on the silicon layer in each active area. An interlevel dielectric layer is deposited overlying the gate electrodes. First contacts are opened through the interlevel dielectric layer to the underlying source and drain regions. A second contact opening is made through the interlevel dielectric layer in each of the active regions wherein the second contact opening contacts both the first trench and one of the second trenches. The first and second contact openings are filled with a conducting layer to complete formation of a silicon-on-insulator device in the fabrication of integrated circuits.

    摘要翻译： 描述了一种在消除浮体效应的同时形成绝缘体上硅MOSFET的新方法。 提供了一种绝缘体上硅衬底，其包括位于硅层下面的氧化物层下面的硅半导体衬底。 第一沟槽部分地被蚀刻穿过硅层而不是蚀刻到下面的氧化物层。 第二沟槽被完全蚀刻通过硅层到下面的氧化物层，其中第二沟槽分离半导体衬底的有源区域，并且其中第一沟槽中的一个位于每个有源区域内。 第一和第二沟槽填充有绝缘层。 栅极电极和相关的源极和漏极区域形成在每个有源区域中的硅层中和硅层上。 沉积覆盖栅电极的层间电介质层。 第一触点通过层间介质层开放到下面的源极和漏极区域。 在每个有源区域中通过层间电介质层形成第二接触开口，其中第二接触开口接触第一沟槽和第二沟槽中的一个沟槽。 第一和第二接触开口填充有导电层，以在集成电路的制造中完成绝缘体上硅器件的形成。

    Simplified method of fabricating a rim phase shift mask
    10.
    发明授权
    Simplified method of fabricating a rim phase shift mask 失效
    制造轮辋相移掩模的简化方法

    公开(公告)号：US06582856B1

    公开(公告)日：2003-06-24

    申请号：US09513872

    申请日：2000-02-28

    申请人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

    发明人： Shyue Fong Quek ,  Ting Cheong Ang ,  Jun Song ,  Sang Yee Loong

    IPC分类号： G03F900

    CPC分类号： G03F1/29

    摘要： A new method of fabricating a rim phase shifting mask is achieved. An opaque layer is provided overlying a transparent substrate. A resist layer is deposited overlying the opaque layer. The resist layer is patterned. The opaque layer and the transparent substrate are etched. The resist layer masks this etching. The opaque layer is etched through during this etching. Notches are thereby etched into the transparent substrate at the edges of the opaque layer. These notches will cause a phase shift in incident light relative to incident light passing through regions in the transparent substrate adjacent to the notches. During this etching, an overetch is performed to remove any mask defects in the transparent substrate. Optionally, the notches may be etched into a phase shifting layer overlying the transparent substrate. An etch stopping layer may also be used in the phase shifting layer embodiment.

    摘要翻译： 实现了制作边缘相移掩模的新方法。 在透明基底上方设置不透明层。 将抗蚀剂层沉积在不透明层上。 抗蚀剂层被图案化。 蚀刻不透明层和透明基板。 抗蚀剂层掩盖该蚀刻。 在该蚀刻期间蚀刻不透明层。 因此，在不透明层的边缘处，凹口被蚀刻到透明基板中。 这些凹口将引起入射光相对于穿过透明衬底中与凹口相邻的区域的入射光的相移。 在该蚀刻期间，执行过蚀刻以去除透明基板中的任何掩模缺陷。 可选地，凹口可被蚀刻到覆盖透明衬底的相移层中。 在相移层实施例中也可以使用蚀刻停止层。