公开(公告)号：US20220271088A1

公开(公告)日：2022-08-25

申请号：US17202296

申请日：2021-03-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Kun-I Chou ,  Ching-Hua Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L43/02

Abstract: A memory array includes at least one strap region having therein a plurality of source line straps and a plurality of word line straps, and at least two sub-arrays having a plurality of staggered, active magnetic storage elements. The at least two sub-arrays are separated by the strap region. A plurality of staggered, dummy magnetic storage elements is disposed within the strap region.

公开(公告)号：US20220263017A1

公开(公告)日：2022-08-18

申请号：US17738001

申请日：2022-05-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L43/02

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a cap layer adjacent to and directly contacting the MTJ, a first inter-metal dielectric (IMD) layer around the MTJ, a top electrode on the MTJ, a metal interconnection under the MTJ, and a second IMD layer around the metal interconnection. Preferably, the cap layer is a single layer structure made of dielectric material and an edge of the cap layer contacts the first IMD layer directly.

公开(公告)号：US20220263016A1

公开(公告)日：2022-08-18

申请号：US17736069

申请日：2022-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L43/02

Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) stack on a substrate; forming a top electrode on the MTJ stack; performing a first patterning process to remove the MTJ stack for forming a first MTJ; forming a first inter-metal dielectric (IMD) layer around the first MTJ; and performing a second patterning process to remove the first MTJ for forming a second MTJ and a third MTJ.

公开(公告)号：US20220115587A1

公开(公告)日：2022-04-14

申请号：US17090859

申请日：2020-11-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Ju-Chun Fan ,  Yi-Yu Lin ,  Ching-Hua Hsu ,  Hung-Yueh Chen

IPC: H01L43/08 ,  H01L27/22 ,  H01L43/02 ,  H01L43/10

Abstract: A semiconductor device includes a substrate, a first dielectric layer, a second dielectric layer, and a third dielectric layer. The first dielectric layer is disposed on the substrate, around a first metal interconnection. The second dielectric layer is disposed on the first dielectric layer, around a via and a second metal interconnection. The second metal interconnection directly contacts the first metal interconnection. The third dielectric layer is disposed on the second dielectric layer, around a first magnetic tunneling junction (MTJ) structure and a third metal interconnection. The third metal interconnection directly contacts the first MTJ structure and the second metal interconnection, and the first MTJ structure directly contacts the via.

公开(公告)号：US20220059618A1

公开(公告)日：2022-02-24

申请号：US17033901

申请日：2020-09-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Kai Hsu ,  Hui-Lin Wang ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Ju-Chun Fan ,  Hung-Yueh Chen

IPC: H01L27/24 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12 ,  H01L45/00

Abstract: A hybrid random access memory for a system-on-chip (SOC), including a semiconductor substrate with a MRAM region and a ReRAM region, a first dielectric layer on the semiconductor substrate, multiple ReRAM cells in the first dielectric layer on the ReRAM region, a second dielectric layer above the first dielectric layer, and multiple MRAM cells in the second dielectric layer on the MRAM region.

公开(公告)号：US11195994B2

公开(公告)日：2021-12-07

申请号：US16689100

申请日：2019-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Chen-Yi Weng ,  Si-Han Tsai ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L43/02 ,  H01L27/22

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

公开(公告)号：US20210296570A1

公开(公告)日：2021-09-23

申请号：US17338632

申请日：2021-06-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A semiconductor device includes: a substrate comprising a magnetic tunneling junction (MTJ) region and a logic region, a MTJ on the MTJ region, a top electrode on the MTJ, a connecting structure on the top electrode, and a first metal interconnection on the logic region. Preferably, the first metal interconnection includes a via conductor on the substrate and a trench conductor, in which a bottom surface of the trench conductor is lower than a bottom surface of the connecting structure.

公开(公告)号：US12274180B2

公开(公告)日：2025-04-08

申请号：US18122730

申请日：2023-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

公开(公告)号：US20240306514A1

公开(公告)日：2024-09-12

申请号：US18126486

申请日：2023-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Che-Wei Chang ,  Ching-Hua Hsu ,  Chen-Yi Weng ,  Po-Kai Hsu

IPC: H10N50/10 ,  H01L23/522 ,  H01L23/528 ,  H10B61/00 ,  H10N50/80

CPC classification number: H10N50/10 ,  H01L23/5226 ,  H01L23/5283 ,  H10B61/00 ,  H10N50/80

Abstract: A magnetic random access memory structure includes a first dielectric layer; a bottom electrode layer disposed on the first dielectric layer; a spin orbit coupling layer disposed on the bottom electrode layer; a magnetic tunneling junction (MTJ) element disposed on the spin orbit coupling layer; a top electrode layer disposed on the MTJ element; a protective layer surrounding the MTJ element and the top electrode layer, and the protective layer masking the spin orbit coupling layer; and a spacer layer surrounding the protective layer.

公开(公告)号：US12063792B2

公开(公告)日：2024-08-13

申请号：US18207654

申请日：2023-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.