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11 条记录 (耗时 0.014 秒)

    MRAM STRUCTURE
    1.
    发明申请
    MRAM STRUCTURE 有权

    公开(公告)号：US20210225414A1

    公开(公告)日：2021-07-22

    申请号：US17224153

    申请日：2021-04-07

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

    IPC分类号： G11C5/06 ,  H01L27/24 ,  H01L27/22

    摘要： A MRAM structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with storage units on corresponding active areas, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

    Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge
    3.
    发明授权
    Method for fabricating semiconductor device including a patterned multi-layered dielectric film with an exposed edge 有权
    一种制造半导体器件的方法，包括具有暴露边缘的图案化多层电介质膜

    公开(公告)号：US09412851B2

    公开(公告)日：2016-08-09

    申请号：US14138153

    申请日：2013-12-23

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Yu-Chun Chang ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kuo-Lung Li ,  Kun-I Chou ,  Chung-Che Huang ,  Chia-Cheng Hsu ,  Mu-Jia Liu

    IPC分类号： H01L21/3205 ,  H01L21/4763 ,  H01L29/66 ,  H01L27/115

    CPC分类号： H01L29/66833 ,  H01L27/1157 ,  H01L27/11573

    摘要： A method for fabricating a semiconductor device includes forming a patterned multi-layered dielectric film on a substrate; forming a patterned stack on the patterned multi-layered dielectric film so that an edge of the patterned multi-layered dielectric film is exposed from the patterned stack; forming a cover layer to cover a part of the substrate and expose the patterned stack and the exposed edge of the patterned multi-layered dielectric film; removing at least a part of the exposed edge of the patterned multi-layered dielectric film by using the cover layer and the patterned stack as an etching mask; and performing an ion implantation process by using the cover layer as an etching mask so as to form a doped region.

    摘要翻译： 一种制造半导体器件的方法包括在衬底上形成图案化的多层电介质膜; 在图案化的多层电介质膜上形成图案化的叠层，使得图案化的多层电介质膜的边缘从图案化的叠层露出; 形成覆盖层以覆盖基板的一部分并暴露图案化的叠层和图案化多层电介质膜的暴露边缘; 通过使用覆盖层和图案化叠层作为蚀刻掩模去除图案化的多层电介质膜的暴露边缘的至少一部分; 以及通过使用覆盖层作为蚀刻掩模进行离子注入工艺以形成掺杂区域。

    Method for manufacturing silicon—oxide—nitride—oxide—silicon (SONOS) non-volatile memory cell
    5.
    发明授权
    Method for manufacturing silicon—oxide—nitride—oxide—silicon (SONOS) non-volatile memory cell 有权
    制造氧化硅 - 氧化物 - 氧化物 - 硅（SONOS）非易失性存储单元的方法

    公开(公告)号：US09202701B1

    公开(公告)日：2015-12-01

    申请号：US14572805

    申请日：2014-12-17

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-I Chou ,  Chi-Cheng Huang ,  Yu-Chun Chang ,  Ling-Hsiu Chou ,  Tseng-Fang Dai ,  Jheng-Jie Huang ,  Ping-Chia Shih

    IPC分类号： H01L21/336 ,  H01L21/28 ,  H01L27/115

    CPC分类号： H01L21/28282 ,  H01L29/66833 ,  H01L29/792

    摘要： A method for manufacturing a silicon-oxide-nitride-oxide-silicon non-volatile memory cell includes following steps. An implant region is formed in a substrate. A first oxide layer, a nitride layer, and a second oxide layer are formed and stacked on the substrate. A density of the second oxide layer is higher than a density of the first oxide layer. A first photoresist pattern is formed on the second oxide layer and corresponding to the implant region. A first wet etching process is then performed to form an oxide hard mask. A second wet etching process is performed to remove the nitride layer exposed by the oxide hard mask to form a nitride pattern. A cleaning process is then performed to remove the oxide hard mask and the first oxide layer exposed by the nitride pattern, and a gate oxide layer is then formed on the nitride pattern.

    摘要翻译： 一种用于制造氧化硅 - 氮化物 - 氧化物 - 硅非易失性存储单元的方法包括以下步骤。 在衬底中形成植入区域。 形成第一氧化物层，氮化物层和第二氧化物层并堆叠在基板上。 第二氧化物层的密度高于第一氧化物层的密度。 第一光致抗蚀剂图案形成在第二氧化物层上并对应于植入区域。 然后进行第一湿法蚀刻工艺以形成氧​​化物硬掩模。 执行第二湿法蚀刻工艺以去除由氧化物硬掩模暴露的氮化物层以形成氮化物图案。 然后进行清洁处理以除去由氮化物图案暴露的氧化物硬掩模和第一氧化物层，然后在氮化物图案上形成栅极氧化物层。

    MAGNETORESISTIVE RANDOM ACCESS MEMORY
    8.
    发明申请
    MAGNETORESISTIVE RANDOM ACCESS MEMORY 审中-公开

    公开(公告)号：US20200083287A1

    公开(公告)日：2020-03-12

    申请号：US16170018

    申请日：2018-10-24

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Kun-I Chou ,  Hung-Yueh Chen

    IPC分类号： H01L27/22 ,  H01L43/08

    摘要： A semiconductor device includes: a first metal-oxide semiconductor (MOS) transistor and a second MOS transistor on a substrate; a magnetic tunneling junction (MTJ) between the first MOS transistor and the second MOS transistor; a first interlayer dielectric (ILD) layer on one side of the MTJ and above the first MOS transistor; and a second ILD layer on another side of the MTJ and above the second MOS transistor.

    Memory layout structure
    9.
    发明授权
    Memory layout structure 有权

    公开(公告)号：US11011210B2

    公开(公告)日：2021-05-18

    申请号：US16592734

    申请日：2019-10-03

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

    IPC分类号： G11C5/06 ,  H01L27/24 ,  H01L27/22

    摘要： A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.

    MEMORY LAYOUT STRUCTURE
    10.
    发明申请
    MEMORY LAYOUT STRUCTURE 有权

    公开(公告)号：US20210065750A1

    公开(公告)日：2021-03-04

    申请号：US16592734

    申请日：2019-10-03

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Po-Kai Hsu ,  Hung-Yueh Chen ,  Kun-I Chou ,  Jing-Yin Jhang ,  Hui-Lin Wang ,  Yu-Ping Wang

    IPC分类号： G11C5/06 ,  H01L27/22 ,  H01L27/24

    摘要： A memory layout structure, which is provided with multiple source lines between active areas, each source line has multiple branches electrically connecting with the active areas at opposite sides in alternating arrangement. Multiple word lines traverse through the active areas to form transistors. Multiple storage units are disposed between the word lines on the active areas in staggered array arrangement, and multiple bit lines electrically connect with all storage units on a corresponding active area, wherein each storage cell includes one of the storage unit, two of the transistors respectively at both sides of the storage unit, and two branches of the source line.