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公开(公告)号：US20240107777A1
公开(公告)日：2024-03-28
申请号：US17964935
申请日：2022-10-13
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Hung-Chan Lin , Chung-Yi Chiu
CPC classification number: H01L27/228 , H01L43/04 , H01L43/06 , H01L43/14
Abstract: An SOT MRAM structure includes a word line. A second source/drain doping region and a fourth source/drain doping region are disposed at the same side of the word line. A first conductive line contacts the second source/drain doping region. A second conductive line contacts the fourth source/drain doping region. The second conductive line includes a third metal pad. A memory element contacts an end of the first conductive line. A second SOT element covers and contacts a top surface of the memory element. The third metal pad covers and contacts part of the top surface of the second SOT element.
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公开(公告)号：US20240032434A1
公开(公告)日：2024-01-25
申请号：US18376840
申请日：2023-10-05
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
Abstract: A manufacturing method of a memory device includes following steps. Memory units are formed on a substrate. Each memory unit includes a first electrode, a second electrode disposed above the first electrode in a vertical direction, and a memory material layer disposed between the first electrode and the second electrode. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a first portion of the non-conformal spacer layer between the memory units in a horizontal direction and a first portion of the conformal spacer layer on the first portion of the conformal spacer layer in the vertical direction. A thickness of a second portion of the non-conformal spacer layer on the second electrode is greater than a thickness of the second portion of the non-conformal spacer layer on the memory material layer.
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公开(公告)号：US11832527B2
公开(公告)日：2023-11-28
申请号：US17705372
申请日：2022-03-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chia-Chang Hsu
Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection.
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公开(公告)号：US11825751B2
公开(公告)日：2023-11-21
申请号：US17377367
申请日：2021-07-15
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
Abstract: A manufacturing method of a memory device includes the following steps. Memory units are formed on a substrate. Each of the memory units includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction. The memory material layer is disposed between the first electrode and the second electrode in the vertical direction. A conformal spacer layer is formed on the memory units. A non-conformal spacer layer is formed on the conformal spacer layer. A first opening is formed penetrating through a sidewall portion of the non-conformal spacer layer and a sidewall portion of the conformal spacer layer in the vertical direction.
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公开(公告)号：US11785867B2
公开(公告)日：2023-10-10
申请号：US17372528
申请日：2021-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
CPC classification number: H10N70/826 , H10B63/00 , H10N70/011 , H10N70/231
Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.
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Patent Agency Ranking
公开(公告)号：US20230210013A1
公开(公告)日：2023-06-29
申请号：US18116305
申请日：2023-03-02
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo
Abstract: A semiconductor device includes a substrate having a logic region and a memory region, a first interlayer dielectric layer on the substrate, and a second interlayer dielectric layer disposed on and directly contacting a top surface of the first interlayer dielectric layer. A portion of the top surface of the first interlayer dielectric layer on the memory region is lower than another portion of the top surface of the first interlayer dielectric layer on the logic region. A memory stack structure is disposed in the first interlayer dielectric layer on the memory region. A passivation layer covers a top surface and sidewalls of the memory stack structure and is in direct contact with the second interlayer dielectric layer. An upper contact structure penetrates through the second interlayer dielectric layer and the passivation layer on the top surface of the memory stack structure and directly contacts the memory stack structure.
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公开(公告)号：US20220399492A1
公开(公告)日：2022-12-15
申请号：US17372528
申请日：2021-07-12
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chung-Yi Chiu
Abstract: A memory device includes a substrate, a memory unit, and a first spacer layer. The memory unit is disposed on the substrate, and the memory unit includes a first electrode, a second electrode, and a memory material layer. The second electrode is disposed above the first electrode in a vertical direction, and the memory material layer is disposed between the first electrode and the second electrode in the vertical direction. The first spacer layer is disposed on a sidewall of the memory unit. The first spacer layer includes a first portion and a second portion. The first portion is disposed on a sidewall of the first electrode, the second portion is disposed on a sidewall of the second electrode, and a thickness of the second portion in a horizontal direction is greater than a thickness of the first portion in the horizontal direction.
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公开(公告)号：US20220376166A1
公开(公告)日：2022-11-24
申请号：US17341316
申请日：2021-06-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Chia-Chang Hsu
Abstract: A semiconductor device includes a substrate, a first magnetic tunnel junction (MTJ) structure, a second MTJ structure, and an interconnection structure. The first MTJ structure, the second MTJ structure, and the interconnection structure are disposed on the substrate. The interconnection structure is located between the first MTJ structure and the second MTJ structure in a first horizontal direction, and the interconnection structure includes a first metal interconnection and a second metal interconnection. The second metal interconnection is disposed on and contacts the first metal interconnection. A material composition of the second metal interconnection is different from a material composition of the first metal interconnection.
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公开(公告)号：US20210028352A1
公开(公告)日：2021-01-28
申请号：US17064614
申请日：2020-10-07
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Meng-Jun Wang , Yi-Wei Tseng , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming an etch stop layer on the first IMD layer; forming a second IMD layer on the etch stop layer; forming a patterned hard mask on the second IMD layer; performing a first etching process to form a contact hole in the second IMD layer for exposing the etch stop layer; performing a second etching process to remove the patterned hard mask; performing a third etching process to remove the etch stop layer and the first IMD layer for exposing the MTJ; and forming a metal interconnection in the contact hole.
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公开(公告)号：US20210020693A1
公开(公告)日：2021-01-21
申请号：US16544923
申请日：2019-08-20
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Chih-Wei Kuo , Tai-Cheng Hou , Yu-Tsung Lai , Jiunn-Hsiung Liao
Abstract: A method for fabricating semiconductor device includes the steps of: forming a first magnetic tunneling junction (MTJ) and a second MTJ on a substrate; forming a first top electrode on the first MTJ and a second top electrode on the second MTJ; forming a passivation layer on the first MTJ and the second MTJ; removing part of the passivation layer so that a top surface of all of the remaining passivation layer is lower than a top surface of the first electrode; and forming a ultra low-k (ULK) dielectric layer on the first MTJ and the second MTJ.
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