公开(公告)号：US20170103300A1

公开(公告)日：2017-04-13

申请号：US15090666

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06N3/04 ,  G06F9/445

CPC分类号： G06F7/49947 ,  G06F1/10 ,  G06F7/483 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06F15/82 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： A neural network unit configurable to first/second/third configurations has N narrow and N wide accumulators, multipliers and adders. Each multiplier performs a narrow/wide multiply on first and second narrow/wide inputs to generate a narrow/wide product. A first adder input receives a corresponding narrow/wide accumulator's output and third input receives a widened corresponding narrow multiplier's narrow product in the third configuration. In the first configuration, each narrow/wide adder performs a narrow/wide addition on the first and second inputs to generate a narrow/wide sum for storage into the corresponding narrow/wide accumulator. In the second configuration, each wide adder performs a wide addition on the first and a second input to generate a wide sum for storage into the corresponding wide accumulator. In the third configuration, each wide adder performs a wide addition on the first, second and third inputs to generate a wide sum for storage into the corresponding wide accumulator.

公开(公告)号：US20170103041A1

公开(公告)日：2017-04-13

申请号：US15090705

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06F15/82 ,  G06F9/38 ,  G06F9/30

CPC分类号： G06F15/82 ,  G06F1/10 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： Functional units of a processor fetch and decode architectural instructions of an architectural program. The architectural instructions are of an architectural instruction set of the processor. An execution unit includes first and second memories, a register and processing units. The first memory holds data in rows with addresses. The second memory holds non-architectural instructions of a non-architectural program. The architectural and non-architectural instruction sets are distinct. The processing units execute the non-architectural program instructions to read data from the first memory, perform operations on the data read from the first memory to generate results, and to write the results to the first memory. The register holds information that indicates progress made by the non-architectural program during execution. The first memory is also readable and writable by the architectural program. The architectural program uses the information to decide where in the first memory to read/write data.

公开(公告)号：US20170102941A1

公开(公告)日：2017-04-13

申请号：US15090801

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS ,  KYLE T. O'BRIEN

IPC分类号： G06F9/30 ,  G06N3/08

CPC分类号： G06F7/49947 ,  G06F1/10 ,  G06F7/483 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06F15/82 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： An output buffer holds N words arranged as N/J mutually exclusive output buffer word groups (OBWG) of J words each. N processing units (PU) are arranged as N/J mutually exclusive PU groups each having an associated OBWG. Each PU has an accumulator, an arithmetic unit, and first and second multiplexed registers each having at least J+1 inputs and an output. A first input receives a memory operand and the other J inputs receive the J words of the associated OBWG. Each accumulator provides its output to a respective output buffer word. Each arithmetic unit performs an operation on the first and second multiplexed register outputs and the accumulator output to generate a result for accumulation into the accumulator. A mask input to the output buffer controls which words, if any, of the N words retain their current value or are updated with their respective accumulator output.

公开(公告)号：US20170102940A1

公开(公告)日：2017-04-13

申请号：US15090665

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06F9/30 ,  G06N3/04

摘要： An array of N processing units (PU) each has: an accumulator; an arithmetic unit performs an operation on first, second and third inputs to generate a result to store in the accumulator, the first input receives the accumulator output; a weight input is received by the second input to the arithmetic unit; a multiplexed register has first and second data inputs, an output received by the third input to the arithmetic unit, and a control input that controls the data input selection. The multiplexed register output is also received by an adjacent PU's multiplexed register second data input. The N PU's multiplexed registers collectively operate as an N-word rotater when the control input specifies the second data input. Respective first/second memories hold W/D rows of N weight/data words and provide the N weight/data words to the corresponding weight/multiplexed register first data inputs of the N PUs.

公开(公告)号：US20170102920A1

公开(公告)日：2017-04-13

申请号：US15090794

申请日：2016-04-05

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： G06F7/499 ,  G06N3/08

CPC分类号： G06F15/82 ,  G06F1/10 ,  G06F7/483 ,  G06F7/49947 ,  G06F9/3001 ,  G06F9/30029 ,  G06F9/30032 ,  G06F9/3004 ,  G06F9/30098 ,  G06F9/30101 ,  G06F9/30189 ,  G06F9/321 ,  G06F9/38 ,  G06F9/3836 ,  G06F9/3867 ,  G06F9/3877 ,  G06F9/3893 ,  G06F9/44505 ,  G06N3/04 ,  G06N3/0445 ,  G06N3/0454 ,  G06N3/063 ,  G06N3/0635 ,  G06N3/08 ,  G06N3/088

摘要： A neural network unit includes a random bit source that generates random bits and a plurality of neural processing units (NPU). Each NPU includes an accumulator into which the NPU accumulates a plurality of products as an accumulated value and a rounder that receives the random bits from the random bit source and stochastically rounds the accumulated value based on a random bit received from the random bit source.

公开(公告)号：US20160380649A1

公开(公告)日：2016-12-29

申请号：US15258867

申请日：2016-09-07

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： G. GLENN HENRY ,  TERRY PARKS

IPC分类号： H03M7/42 ,  H03M7/30

CPC分类号： H03M7/42 ,  H03M7/3086 ,  H03M7/6017 ,  H03M7/6088

摘要： A hardware data compressor that compresses an input block of characters by replacing strings of characters in the input block with back pointers to matching strings earlier in the input block. A hash table is used in searching for the matching strings in the input block. A plurality of hash index generators each employs a different hashing algorithm on an initial portion of the strings of characters to be replaced to generate a respective index. The hardware data compressor also includes an indication of a type of the input block of characters. A selector selects the index generated by of one of the plurality hash index generators to index into the hash table based on the type of the input block.

公开(公告)号：US20160350126A1

公开(公告)日：2016-12-01

申请号：US14889229

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： GERARD M. COL ,  COLIN EDDY ,  G. GLENN HENRY

IPC分类号： G06F9/38 ,  G06F9/30 ,  G06F12/1009 ,  G06F12/0831 ,  G06F1/32 ,  G06F12/0875

CPC分类号： G06F9/3855 ,  G06F1/3228 ,  G06F1/3296 ,  G06F9/30043 ,  G06F9/30101 ,  G06F9/38 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3861 ,  G06F12/0831 ,  G06F12/0875 ,  G06F12/1009

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include a system memory that is accessed via a memory bus, the system memory comprising one or more page tables, configured to store one or more mappings between virtual addresses and physical addresses.

公开(公告)号：US20160350122A1

公开(公告)日：2016-12-01

申请号：US14889339

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： GERARD M. COL ,  COLIN EDDY ,  G. GLENN HENRY

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of prescribed resources includes system memory, coupled to the out-of-order processor via a memory bus, where the specified load micro instruction is known to resolve to write combining memory space in the system memory.

公开(公告)号：US20160350121A1

公开(公告)日：2016-12-01

申请号：US14889281

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： GERARD M. COL ,  COLIN EDDY ,  G. GLENN HENRY

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The plurality of non-core resources includes an off-core cache memory, configured to store memory operands which may have been cached from a system memory that are not present in one or more on-core cache memories.

公开(公告)号：US20160350119A1

公开(公告)日：2016-12-01

申请号：US14889223

申请日：2014-12-14

申请人： VIA ALLIANCE SEMICONDUCTOR CO., LTD.

发明人： GERARD M. COL ,  COLIN EDDY ,  G. GLENN HENRY

IPC分类号： G06F9/38 ,  G06F9/30

CPC分类号： G06F9/3838 ,  G06F9/30043 ,  G06F9/30083 ,  G06F9/30101 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3861 ,  G06F9/3863 ,  G06F13/24 ,  Y02D10/14

摘要： An apparatus including first and second reservation stations. The first reservation station dispatches a load micro instruction, and indicates on a hold bus if the load micro instruction is a specified load micro instruction directed to retrieve an operand from a prescribed resource other than on-core cache memory. The second reservation station is coupled to the hold bus, and dispatches one or more younger micro instructions therein that depend on the load micro instruction for execution after a number of clock cycles following dispatch of the first load micro instruction, and if it is indicated on the hold bus that the load micro instruction is the specified load micro instruction, the second reservation station is configured to stall dispatch of the one or more younger micro instructions until the load micro instruction has retrieved the operand. The resources include an advanced programmable interrupt controller (APIC), configured to perform interrupt operations.