公开(公告)号：US06407640B1

公开(公告)日：2002-06-18

申请号：US09667901

申请日：2000-09-22

申请人： Vladimir Aparin ,  Peter Jivan Shah

发明人： Vladimir Aparin ,  Peter Jivan Shah

IPC分类号： H03F3191

CPC分类号： H03F3/191 ,  H03F1/22 ,  H03F1/302 ,  H03F2200/294 ,  H03F2200/372

摘要： A two-stage stacked high IIP3 LNA with low current consumption is presented. Low-impedance bias terminations and optimum inter-stage match are used for IIP3 enhancement. A new graphical design technique is introduced for optimizing the linearity trade-offs in two-stage amplifiers and for optimizing the on-chip inter-stage matching network. Also, novel active circuits for bias modulation suppression are discussed. The LNA has been fabricated in a commercial SiGe BiCMOS technology, and measurement results are presented.

摘要翻译： 提出了一种具有低电流消耗的两级堆叠高IIP3 LNA。 低阻抗偏置端子和最佳级间匹配用于IIP3增强。 引入了一种新的图形设计技术，用于优化两级放大器中的线性折中和优化片上级间匹配网络。 此外，讨论了用于偏置调制抑制的新颖的有源电路。 LNA已经以商业SiGe BiCMOS技术制造，并提供了测量结果。

公开(公告)号：US09287886B2

公开(公告)日：2016-03-15

申请号：US12366441

申请日：2009-02-05

申请人： Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

发明人： Steven C. Ciccarelli ,  Frederic Bossu ,  Vladimir Aparin ,  Kevin H. Wang

IPC分类号： H04B1/40 ,  H03L7/197

CPC分类号： H03L7/1974

摘要： Within a receiver, the frequency of a comparison reference clock signal supplied to a fractional-N Phase-Locked Loop (PLL) is dynamically changed such that undesirable reciprocal mixing of reference spurs with known jammers (for example, transmit leakage) is minimized. As the transmit channel changes within a band, and as the transmit leakage frequency changes, a circuit changes the frequency of the comparison reference clock signal such that reference spurs generated by the PLL are moved in frequency so that they do not reciprocally mix with transmitter leakage in undesirable ways. In a second aspect, the PLL is operable either as an integer-N PLL or a fractional-N PLL. In low total receive power situations, the PLL operates as an integer-N PLL to reduce receiver susceptibility to fractional-N spurs. In a third aspect, jammer detect information is used to determine the comparison reference clock signal frequency.

摘要翻译： 在接收机内，提供给分数N锁相环（PLL）的比较参考时钟信号的频率被动态地改变，使得具有已知干扰的参考杂波（例如，传输泄漏）的不期望的相互混合被最小化。 当发射信道在频带内变化时，并且随着发射泄漏频率的变化，电路改变比较参考时钟信号的频率，使得PLL产生的参考杂波频率移动，使得它们不与发射机泄漏相互混合 以不良的方式。 在第二方面，PLL可以作为整数N个PLL或分数N PLL来操作。 在低总接收功率情况下，PLL作为整数N PLL进行操作，以减少接收机对分数N个杂散的敏感性。 在第三方面，使用干扰检测信息来确定比较参考时钟信号频率。

公开(公告)号：US20130204820A1

公开(公告)日：2013-08-08

申请号：US13369080

申请日：2012-02-08

申请人： Jason Frank Hunzinger ,  Vladimir Aparin

发明人： Jason Frank Hunzinger ,  Vladimir Aparin

IPC分类号： G06N3/08

CPC分类号： G06N3/049 ,  G06N3/08

摘要： Certain aspects of the present disclosure provide methods and apparatus for spiking neural computation of general linear systems. One example aspect is a neuron model that codes information in the relative timing between spikes. However, synaptic weights are unnecessary. In other words, a connection may either exist (significant synapse) or not (insignificant or non-existent synapse). Certain aspects of the present disclosure use binary-valued inputs and outputs and do not require post-synaptic filtering. However, certain aspects may involve modeling of connection delays (e.g., dendritic delays). A single neuron model may be used to compute any general linear transformation x=AX+BU to any arbitrary precision. This neuron model may also be capable of learning, such as learning input delays (e.g., corresponding to scaling values) to achieve a target output delay (or output value). Learning may also be used to determine a logical relation of causal inputs.

摘要翻译： 本公开的某些方面提供了用于通用线性系统的神经计算的方法和装置。 一个示例方面是在尖峰之间的相对定时中编码信息的神经元模型。 然而，突触重量是不必要的。 换句话说，连接可能存在（显着突触）或不存在（不重要或不存在突触）。 本公开的某些方面使用二进制值输入和输出，并且不需要突触后过滤。 然而，某些方面可能涉及对连接延迟的建模（例如树枝状延迟）。 可以使用单个神经元模型来计算任何通用线性变换x = AX + BU到任意精度。 该神经元模型还可能能够学习，例如学习输入延迟（例如，对应于缩放值）以实现目标输出延迟（或输出值）。 学习也可用于确定因果输入的逻辑关系。

公开(公告)号：US20130204819A1

公开(公告)日：2013-08-08

申请号：US13368994

申请日：2012-02-08

申请人： Jason Frank Hunzinger ,  Vladimir Aparin

发明人： Jason Frank Hunzinger ,  Vladimir Aparin

IPC分类号： G06F15/18

CPC分类号： G06N3/049 ,  G06N3/08

摘要： Certain aspects of the present disclosure provide methods and apparatus for spiking neural computation of general linear systems. One example aspect is a neuron model that codes information in the relative timing between spikes. However, synaptic weights are unnecessary. In other words, a connection may either exist (significant synapse) or not (insignificant or non-existent synapse). Certain aspects of the present disclosure use binary-valued inputs and outputs and do not require post-synaptic filtering. However, certain aspects may involve modeling of connection delays (e.g., dendritic delays). A single neuron model may be used to compute any general linear transformation x=AX+BU to any arbitrary precision. This neuron model may also be capable of learning, such as learning input delays (e.g., corresponding to scaling values) to achieve a target output delay (or output value). Learning may also be used to determine a logical relation of causal inputs.

公开(公告)号：US20130117209A1

公开(公告)日：2013-05-09

申请号：US13292161

申请日：2011-11-09

申请人： Vladimir Aparin

发明人： Vladimir Aparin

IPC分类号： G06N3/08

CPC分类号： G06N3/0472 ,  G06N3/04 ,  G06N3/063 ,  G06N3/08

摘要： Certain aspects of the present disclosure support a technique for utilizing a memory in probabilistic manner to store information about weights of synapses of a neural network.

摘要翻译： 本公开的某些方面支持以概率方式利用存储器来存储关于神经网络的突触的权重的信息的技术。

公开(公告)号：US08433665B2

公开(公告)日：2013-04-30

申请号：US12831594

申请日：2010-07-07

申请人： Yi Tang ,  Jeffrey A. Levin ,  Vladimir Aparin ,  Venkat Rangan

发明人： Yi Tang ,  Jeffrey A. Levin ,  Vladimir Aparin ,  Venkat Rangan

IPC分类号： G06F15/18

CPC分类号： G06N3/0635 ,  G06N3/049

摘要： The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.

摘要翻译： 本公开提出了三忆阻突触的实施，其中突触强度的调整基于具有多巴胺信号传导的尖峰时间依赖性可塑性（STDP）。

公开(公告)号：US08331897B2

公开(公告)日：2012-12-11

申请号：US12192933

申请日：2008-08-15

申请人： Namsoo Kim ,  Prasad S. Gudem ,  Vladimir Aparin

发明人： Namsoo Kim ,  Prasad S. Gudem ,  Vladimir Aparin

IPC分类号： H04B1/26

CPC分类号： H03D7/163 ,  H03D7/1466 ,  H03D7/166

摘要： A communication channel has a highly linear switched current mixer that incorporates passive filtering (e.g., low pass, notch) for improved transmitting (Tx) and receiving (Rx) with adding external filtering components. A high IIP2 (input referenced second order intercept point) of the receiver at the Tx offset is essential to avoid corrupting the system's sensitivity performance, and a high triple beat (TB) is required to avoid sensitivity degradation due to transmitter leakage. Thanks to the embedded filtering in the mixer and the active post-distortion (APD) method in a low noise amplifier (LNA), the required high linearity is achieved with low noise figure and power consumption, overcoming transmitter power leakage without the use of a SAW (surface acoustic wave) filter.

摘要翻译： 通信通道具有高度线性的开关电流混频器，其结合无源滤波（例如，低通，陷波），用于增加外部滤波组件以改善发射（Tx）和接收（Rx）。 接收机在Tx偏移处的高IIP2（输入参考二阶截取点）对于避免破坏系统的灵敏度性能至关重要，并且需要高三重（TB）以避免由于发射机泄漏导致的灵敏度劣化。 由于混频器中的嵌入式滤波器和低噪声放大器（LNA）中的有源后失真（APD）方法，所需的高线性度可通过低噪声系数和功耗实现，克服发射机功率泄漏而不使用 SAW（表面声波）滤波器。

公开(公告)号：US20120303567A1

公开(公告)日：2012-11-29

申请号：US13115158

申请日：2011-05-25

申请人： Vladimir Aparin

发明人： Vladimir Aparin

IPC分类号： G06N3/063

CPC分类号： G06N3/063 ,  G06N3/0445

摘要： Certain aspects of the present disclosure present a technique for primary visual cortex (V1) cell training and operation. The present disclosure proposes a model structure of V1 cells and retinal ganglion cells (RGCs), and an efficient method of training connectivity between these two layers of cells such that the proposed method leads to an autonomous formation of feature detectors within the V1 layer. The proposed approach enables a hardware-efficient and biological-plausible implementation of image recognition and motion detection systems.

摘要翻译： 本公开的某些方面提供了用于初级视皮层（V1）细胞训练和操作的技术。 本公开提出了V1细胞和视网膜神经节细胞（RGC）的模型结构，以及训练这两层细胞之间的连通性的有效方法，使得所提出的方法导致在V1层内自主形成特征检测器。 所提出的方法使得能够实现图像识别和运动检测系统的硬件效率和生物可靠性。

公开(公告)号：US08135348B2

公开(公告)日：2012-03-13

申请号：US11691737

申请日：2007-03-27

申请人： Vladimir Aparin

发明人： Vladimir Aparin

IPC分类号： H04B1/00 ,  H04B15/00

CPC分类号： H04B1/525

摘要： This disclosure describes techniques for reducing adverse effects of transmit signal leakage in a full-duplex, wireless communication system. The disclosure describes techniques for reducing adverse effects of second order distortion and cross-modulation distortion of transmit signal leakage from a transmitter via a duplexer. The techniques may be effective in rejecting at least a portion of a transmit leakage signal, thereby reducing or eliminating distortion. The adaptive filter may include an estimator circuit that generates a transmit leakage signal estimate. A summer subtracts the estimate from the received signal to cancel transmit leakage and produce an output signal. The estimator circuit generates the transmit leakage signal estimate based on a reference signal and feedback from the output signal. The reference signal approximates the carrier signal used to generate the transmit signal in the transmitter. The reference signal may be provided by the same oscillator used to produce the transmit carrier signal.

摘要翻译： 本公开描述了用于减少全双工无线通信系统中的发射信号泄漏的不利影响的技术。 本公开描述了用于减少来自发射机的双工器的发射信号泄漏的二阶失真和交叉调制失真的不利影响的技术。 这些技术可以有效地拒绝发射泄漏信号的至少一部分，从而减少或消除失真。 自适应滤波器可以包括产生发射泄漏信号估计的估计器电路。 一个夏天从接收到的信号中减去估计值以消除发射泄漏并产生一个输出信号。 估计器电路基于参考信号和来自输出信号的反馈产生发射泄漏信号估计。 参考信号近似于用于在发射机中产生发射信号的载波信号。 参考信号可以由用于产生发射载波信号的相同振荡器提供。

公开(公告)号：US20120011093A1

公开(公告)日：2012-01-12

申请号：US12831871

申请日：2010-07-07

申请人： Vladimir Aparin ,  Subramaniam Venkatraman

发明人： Vladimir Aparin ,  Subramaniam Venkatraman

IPC分类号： G06N3/063

CPC分类号： G06N3/049 ,  G06N3/0472 ,  G06N3/063

摘要： Certain embodiments of the present disclosure support implementation of a digital neural processor with discrete-level synapses and probabilistic synapse weight training.

摘要翻译： 本公开的某些实施例支持具有离散级突触和概率突触重量训练的数字神经处理器的实现。