-
公开(公告)号：US07754505B1
公开(公告)日：2010-07-13
申请号：US12284290
申请日：2008-09-19
IPC分类号： H01L21/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译： 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。
-
公开(公告)号：US07705403B1
公开(公告)日：2010-04-27
申请号：US11324455
申请日：2006-01-03
IPC分类号： H01L23/62
CPC分类号： H01L27/0262 , H01L29/87
摘要： In a LVTSCR or snapback NMOS ESD structure, low voltage protection as well as higher voltage protection is provided by introducing a floating gate that capacitively couples with the control gate of the ESD structure and programming the floating gate to have different charges on it as desired.
摘要翻译： 在LVTSCR或快速恢复型NMOS ESD结构中，通过引入与ESD结构的控制栅极电容耦合的浮动栅极，并根据需要对浮动栅极进行编程，从而提供低电压保护以及更高的电压保护。
-
公开(公告)号：US07528012B1
公开(公告)日：2009-05-05
申请号：US11508495
申请日：2006-08-22
IPC分类号： H01L21/00
CPC分类号： H01L29/78606 , H01L23/3677 , H01L23/481 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for a heat sink to dissipate the heat sourced by the encapsulated transistors in a SOI wafer. The apparatus includes a transistor formed in the active silicon layer of the wafer. The active surface is formed over an oxide layer and a bulk silicon layer. A heat sink is formed in the bulk silicon layer and configured to sink heat through the bulk silicon layer, to the back surface of the wafer. After the transistor is fabricated, the heat sink is formed by masking, patterning and etching the back surface of the wafer to form plugs in the bulk silicon layer. The plug extends through the thickness of the bulk layer to the oxide layer. Thereafter, the plug is filled with a thermally conductive material, such as a metal or DAG (thermally conductive paste). During operation, heat from the transistor is dissipated through the heat sink. In various embodiments of the invention, the plug hole is formed using either an anisotropic plasma or wet etch.
摘要翻译： 散热器散热由SOI晶片中的封装晶体管产生的热量的装置和方法。 该装置包括形成在晶片的有源硅层中的晶体管。 活性表面形成在氧化物层和体硅层上。 在体硅层中形成散热器，并且构造成将热量通过体硅层吸收到晶片的背面。 在制造晶体管之后，通过掩模，图案化和蚀刻晶片的背面来形成散热器，以在体硅层中形成插塞。 塞子延伸穿过本体层的厚度到氧化物层。 此后，塞子填充有导热材料，例如金属或DAG（导热浆）。 在运行期间，来自晶体管的热量通过散热器消散。 在本发明的各种实施例中，插塞孔使用各向异性等离子体或湿蚀刻形成。
-
公开(公告)号：US07462874B1
公开(公告)日：2008-12-09
申请号：US11403516
申请日：2006-04-13
IPC分类号： H01L33/00
CPC分类号： H01L33/387 , H01L33/04 , H01L33/08
摘要： A silicon-based light emitting structure is formed as a high density array of light-emitting p-n junctions that substantially increases the intensity of the light emitted in a planar region. The p-n junctions are formed using standard CMOS processing methods, and emit light in response to applied voltages that generate avalanche breakdown and an avalanche current.
摘要翻译： 形成硅基发光结构作为发光p-n结的高密度阵列，其显着增加在平坦区域中发射的光的强度。 使用标准CMOS处理方法形成p-n结，并响应于产生雪崩击穿和雪崩电流的施加电压而发光。
-
公开(公告)号：US07422952B1
公开(公告)日：2008-09-09
申请号：US11799954
申请日：2007-05-03
IPC分类号： H01L21/331 , H01L21/8222
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译： 将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。 将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。
-
公开(公告)号：US07375579B1
公开(公告)日：2008-05-20
申请号：US11198796
申请日：2005-08-04
IPC分类号： H01H37/76
摘要： In a fuse-based programmable circuit block, the poly-fuse is burned out by making use of a snapback device connected in series with the poly-fuse.
摘要翻译： 在基于熔丝的可编程电路块中，通过使用与多熔丝串联连接的快速恢复装置将多晶硅熔断器烧掉。
-
公开(公告)号：US07375393B1
公开(公告)日：2008-05-20
申请号：US11044511
申请日：2005-01-27
IPC分类号： H01L29/788
CPC分类号： H01L29/7881 , H01L29/42324
摘要： An electrical shield is provided in a non-volatile memory (NVM) cell structure to protect the cell's floating gate from any influence resulting from charge redistribution in the vicinity of the floating gate during a programming operation. The shield may be created from the second polysilicon layer or other conductive material covering the floating gate. The shield may be grounded. Alternately, it may be connected to the cell's control gate electrode resulting in better coupling between the floating gate and the control gate. It is not necessary that the shield cover the floating gate completely, the necessary protective effect is achieved if the coupling to the dielectric layers surrounding the floating gate is reduced.
-
公开(公告)号：US07298653B1
公开(公告)日：2007-11-20
申请号：US10873872
申请日：2004-06-21
IPC分类号： G11C11/34
CPC分类号： G11C29/02 , G11C16/04 , G11C16/12 , G11C29/021 , G11C29/028 , G11C29/50004
摘要： In an EEPROM array the cells are pre-charged or pre-erased so that they will respond uniformly to the same read voltage level. By clearly defining the threshold voltage for the cells in their erased states and in their programmed states, it is possible to define more than one read voltage and thus provide cells that an store multiple values and even analog values.
摘要翻译： 在EEPROM阵列中，单元被预充电或预擦除，使得它们将均匀地响应于相同的读取电压电平。 通过明确定义其擦除状态和编程状态下的单元的阈值电压，可以定义多个读取电压，从而提供存储多个值和甚至模拟值的单元。
-
公开(公告)号：US07221608B1
公开(公告)日：2007-05-22
申请号：US10957986
申请日：2004-10-04
IPC分类号： G11C7/00
CPC分类号： G11C11/406 , G11C11/403 , G11C2211/4065
摘要： The snapback characteristics of the parasitic NPN structure inside an NMOS device are used to write and store information in the device by periodically triggering the device from the high impedance state to the low impedance state using the self turn-on characteristics of the device under elevated voltage. To minimize power consumption, and thus overheating, in the “on” state, a pulsed mode operation is combined with dV/dt triggering powering the device at a constant Vdd pulse amplitude.
摘要翻译： NMOS器件内的寄生NPN结构的快速恢复特性用于通过在高电压下使器件的自启动特性周期性地将器件从高阻抗状态触发到低阻抗状态来将信息写入和存储在器件中 。 为了最小化功率消耗并因此过热，在“导通”状态下，将脉冲模式操作与dV / dt触发相结合，以恒定的Vdd脉冲幅度向器件供电。
-
公开(公告)号：US07196361B1
公开(公告)日：2007-03-27
申请号：US10734921
申请日：2003-12-12
IPC分类号： H01R29/747 , H01R29/87
CPC分类号： H01L27/0262
摘要： In a high voltage ESD protection solution, a plurality of DIACs are connected together to define a cascaded structure with isolation regions provided to prevent n-well and p-well punch through. An p-ring surrounds the DIACs and provides a ground for the substrate in which the DIACs are formed.
摘要翻译： 在高电压ESD保护解决方案中，多个DIAC连接在一起以限定提供隔离区域的级联结构，以防止n阱和p阱穿通。 一个p环环绕着DIAC，并为形成DIAC的衬底提供了一个接地。
-
-
-
-
-
-
-
-
-
搜索结果
282 条记录 (耗时 0.027 秒)
