-
公开(公告)号：US07209503B1
公开(公告)日：2007-04-24
申请号：US10838671
申请日：2004-05-03
IPC分类号： H01S5/00
CPC分类号： H01L27/1446 , H01L27/146
摘要： An integrated circuit is powered by exposing conductive regions, such as the p+ source regions of the PMOS transistors that are formed to receive a supply voltage, to light energy from a light source. The conductive regions function as photodiodes that produce voltages on the conductive regions via the photovoltaic effect.
摘要翻译： 集成电路通过将形成为接收电源电压的PMOS晶体管的p +源极区域等导电区域暴露于来自光源的光能来供电。 导电区域用作通过光电效应在导电区域上产生电压的光电二极管。
-
公开(公告)号：US07113427B1
公开(公告)日：2006-09-26
申请号：US11076711
申请日：2005-03-09
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/12 , G11C16/3459 , H01L27/115 , H01L29/7881
摘要： NVM cell for storing three levels of charge: one erased and two programmed states. The cell comprises a transistor structure providing a gate current versus gate voltage curve having a shape with a flat region or a second peak. To provide such a structure, one embodiment combines two parallel transistors having different threshold voltages, and another embodiment uses one transistor with variable doping. The gate current curve provides two programming zones. Programming the first state includes applying a voltage across a channel, ramping up a gate voltage in the first programming zone, followed by ramping it back down. Programming the second state comprises applying a voltage across a channel, ramping up a gate voltage past the first programming zone and into the second programming zone, followed by ramping it back down. Ramping the voltage back down may optionally be preceded by turning off the voltage across the channel.
摘要翻译： 用于存储三个电荷电平的NVM单元：一个擦除和两个编程状态。 该单元包括提供具有平坦区域或第二峰值的形状的栅极电流对栅极电压曲线的晶体管结构。 为了提供这样的结构，一个实施例组合了具有不同阈值电压的两个并联晶体管，另一实施例使用一个具有可变掺杂的晶体管 栅极电流曲线提供两个编程区域。 对第一状态进行编程包括在一个通道上施加电压，使第一个编程区中的栅极电压升高，然后将其向下斜坡。 对第二状态进行编程包括在通道上施加电压，将栅极电压升高到第一编程区并进入第二编程区，然后将其向下斜坡。 可以选择先将电压降低，然后关闭通道上的电压。
-
公开(公告)号：US07075341B1
公开(公告)日：2006-07-11
申请号：US10823455
申请日：2004-04-13
IPC分类号： H03B1/00
CPC分类号： H01L27/0266
摘要： A linear time-driver circuit is provided that consumes low space on-chip. The time-driver circuit is based upon the small capacitor charge of the merged region of a 5V tolerant cascaded NMOS device, a single gate device and a zener diode.
摘要翻译： 提供消耗片上低空间的线性时间驱动电路。 时间驱动电路基于5V容限级联NMOS器件，单栅极器件和齐纳二极管的合并区域的小电容器电荷。
-
4.发明授权Efficient method of PMOS stacked-gate memory cell programming utilizing feedback control of substrate current 有权利用衬底电流的反馈控制的PMOS堆叠栅极存储器单元编程的有效方法公开(公告)号：US06903979B1
公开(公告)日：2005-06-07
申请号：US10664758
申请日：2003-09-17
CPC分类号： G11C16/10
摘要： A method of programming a PMOS stacked gate memory cell is provided that utilizes the correlation between injection current and substrate current during the programming cycle to provide a feedback correction to the control gate of the memory cell to compensate for the negative potential shift on the floating gate as a result of its charging time.
摘要翻译： 提供了一种编程PMOS堆叠栅极存储单元的方法，其利用在编程周期期间的注入电流和衬底电流之间的相关性来向存储器单元的控制栅极提供反馈校正，以补偿浮置栅极上的负电位移位 作为其充电时间的结果。
-
公开(公告)号：US07259411B1
公开(公告)日：2007-08-21
申请号：US10728132
申请日：2003-12-04
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L21/823885 , H01L21/823487 , H01L29/0653 , H01L29/0657 , H01L29/41741 , H01L29/66666 , H01L29/7827
摘要： A vertical MOS transistor has a source region, a channel region, and a drain region that are vertically stacked, and a trench that extends from the top surface of the drain region through the drain region, the channel region, and partially into the source region. The vertical MOS transistor also has an insulation layer that lines the trench, and a conductive gate region that contacts the insulation layer to fill up the trench.
摘要翻译： 垂直MOS晶体管具有垂直堆叠的源极区域，沟道区域和漏极区域以及从漏极区域的顶表面延伸穿过漏极区域，沟道区域并且部分地延伸到源极区域的沟槽 。 垂直MOS晶体管还具有对沟槽进行排列的绝缘层，以及接触绝缘层以填充沟槽的导电栅极区域。
-
公开(公告)号：US07221036B1
公开(公告)日：2007-05-22
申请号：US11129957
申请日：2005-05-16
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/7322 , H01L27/0259 , H01L29/0821
摘要： A ballasting region is placed between the base region and the collector contact of a bipolar junction transistor to relocate a hot spot away from the collector contact of the transistor. Relocating the hot spot away from the collector contact prevents the collector contact from melting during an electrostatic discharge (ESD) pulse.
摘要翻译： 将一个压载区域放置在双极结晶体管的基极区域和集电极触点之间，以将热点移离晶体管的集电极触点。 将热点从集电极接触点移开可防止集电极接触在静电放电（ESD）脉冲期间熔化。
-
公开(公告)号：US07180379B1
公开(公告)日：2007-02-20
申请号：US10838485
申请日：2004-05-03
IPC分类号： G01N21/00
CPC分类号： G06F1/105
摘要： A synchronous clock signal is generated in a large number of local clock circuits at the same time by exposing photoconductive regions in each local clock circuit to a pulsed light source that operates at a fixed frequency. The photoconductive regions generate photoconductive currents which are sufficient to cause a logic inverter to switch states.
摘要翻译： 通过将每个本地时钟电路中的光电导区域暴露于以固定频率工作的脉冲光源，同时在多个本地时钟电路中产生同步时钟信号。 光电导区产生足以导致逻辑逆变器切换状态的光电流。
-
公开(公告)号：US07911869B1
公开(公告)日：2011-03-22
申请号：US11198688
申请日：2005-08-05
摘要： In a programmable circuit making use of fuse cells, a snapback NMOS or NPN transistor or SCR without reversible snapback capability is used as an anti-fuse, and programming comprises biasing the control electrode of the transistor to cause the transistor to go into snapback mode.
摘要翻译： 在使用熔丝单元的可编程电路中，使用不具有可逆快速恢复能力的快速恢复NMOS或NPN晶体管或SCR作为反熔丝，并且编程包括偏置晶体管的控制电极以使晶体管进入快速恢复模式。
-
公开(公告)号：US07057867B1
公开(公告)日：2006-06-06
申请号：US10851516
申请日：2004-05-21
IPC分类号： H02H9/00
CPC分类号： H01L27/0259 , H01L27/0266
摘要： Electrostatic discharge (ESD) protection clamp circuitry including current tunneling circuitry to provide control current for controlling current shunting circuitry for shunting ESD current from the protected signal terminal.
摘要翻译： 静电放电（ESD）保护钳位电路，包括电流隧道电路，以提供控制电流，用于控制电流分流电路，用于从受保护的信号端子分流ESD电流。
-
公开(公告)号：US06985386B1
公开(公告)日：2006-01-10
申请号：US10895713
申请日：2004-07-08
IPC分类号： G11C16/04
CPC分类号： G11C16/0416 , G11C2216/10 , H01L27/115 , H01L27/11521 , H01L27/11558
摘要： A method of programming a nonvolatile memory cell in which a ramped control voltage is used to obtain the desired voltage on the storage node.
摘要翻译： 一种非易失性存储单元的编程方法，其中使用斜坡控制电压来获得存储节点上的期望电压。
-
-
-
-
-
-
-
-
-
搜索结果
282 条记录 (耗时 0.024 秒)
