公开(公告)号：US20140006753A1

公开(公告)日：2014-01-02

申请号：US13995453

申请日：2011-12-22

申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Kirk S. Yap ,  James D. Guilford ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC分类号： H04L9/28

CPC分类号： H04L9/0631 ,  G06F9/30007 ,  G06F9/3001 ,  G06F9/30036 ,  H04L9/0643

摘要： A method is described. The method includes iteratively performing for each position in a result matrix stored in a third register, multiplying a value at a matrix position stored in a first register with a value at a matrix position stored in a second register to obtain a first multiplicative value, where the positions in the first register and the second register are determined by the position in the result matrix and performing an exclusive or (XOR) operation with the first multiplicative value and a value stored at a result matrix position stored in the third register to obtain a result value.

摘要翻译： 描述了一种方法。 该方法包括对存储在第三寄存器中的结果矩阵中的每个位置迭代执行，将存储在第一寄存器中的矩阵位置处的值乘以存储在第二寄存器中的矩阵位置处的值，以获得第一乘法值，其中 第一寄存器和第二寄存器中的位置由结果矩阵中的位置确定，并且执行具有第一乘法值的异或（XOR）操作和存储在存储在第三寄存器中的结果矩阵位置处的值以获得 结果值。

公开(公告)号：US20130290285A1

公开(公告)日：2013-10-31

申请号：US13995236

申请日：2011-11-01

申请人： Vinodh Gopal ,  James D. Guilford ,  Schuyler Eldridge ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Wajdi K. Feghali

发明人： Vinodh Gopal ,  James D. Guilford ,  Schuyler Eldridge ,  Gilbert M. Wolrich ,  Erdinc Ozturk ,  Wajdi K. Feghali

IPC分类号： G06F17/30

CPC分类号： G06F17/30303 ,  G06F17/30306 ,  G06F17/3033

摘要： In one embodiment, circuitry may generate digests to be combined to produce a hash value. The digests may include at least one digest and at least one other digest generated based at least in part upon at least one CRC value and at least one other CRC value. The circuitry may include cyclical redundancy check (CRC) generator circuitry to generate the at least one CRC value based at least in part upon at least one input string. The CRC generator circuitry also may generate the at least one other CRC value based least in part upon at least one other input string. The at least one other input string resulting at least in part from at least one pseudorandom operation involving, at least in part, the at least one input string. Many modifications, variations, and alternatives are possible without departing from this embodiment.

摘要翻译： 在一个实施例中，电路可以生成待组合的摘要以产生散列值。 摘要可以至少部分地基于至少一个CRC值和至少一个其它CRC值来生成至少一个摘要和至少一个其他摘要。 电路可以包括循环冗余校验（CRC）发生器电路，以至少部分地基于至少一个输入串来生成至少一个CRC值。 CRC发生器电路还可以至少部分地基于至少一个其他输入串来生成至少一个其它CRC值。 所述至少一个其他输入字符串至少部分地由至少一个涉及至少一个输入字符串的伪随机操作产生。 在不脱离本实施例的情况下，可以进行许多修改，变型和替换。

公开(公告)号：US20130275722A1

公开(公告)日：2013-10-17

申请号：US13976184

申请日：2011-12-13

申请人： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

发明人： Kirk S. Yap ,  Gilbert M. Wolrich ,  James D. Guilford ,  Vinodh Gopal ,  Erdinc Ozturk ,  Sean M. Gulley ,  Wajdi K. Feghali ,  Martin G. Dixon

IPC分类号： G06F9/30

CPC分类号： G06F9/30145 ,  H04L9/0643 ,  H04L2209/122

摘要： A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

摘要翻译： 处理器包括多个寄存器，指令解码器，用于接收处理表示KECCAK散列算法的KECCAK状态的数据的KECCAK状态立方体的指令，以将KECCAK状态立方体分割成多个子多维数据集，并存储子管道 分别在多个寄存器中，以及执行单元，其耦合到指令解码器，以向量方式分别存储在多个寄存器中的多个子区上执行KECCAK散列算法。

公开(公告)号：US20100332578A1

公开(公告)日：2010-12-30

申请号：US12459152

申请日：2009-06-26

申请人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Erdinc Ozturk ,  Martin G. Dixon

发明人： Vinodh Gopal ,  Gilbert M. Wolrich ,  Wajdi K. Feghali ,  James D. Guilford ,  Erdinc Ozturk ,  Martin G. Dixon

IPC分类号： G06F7/52 ,  G06F12/08 ,  G06F7/50 ,  H04L9/30

CPC分类号： G06F7/72 ,  G06F12/0802 ,  G06F12/14 ,  G06F2207/7261

摘要： A time-invariant method and apparatus for performing modular reduction that is protected against cache-based and branch-based attacks is provided. The modular reduction technique adds no performance penalty and is side-channel resistant. The side-channel resistance is provided through the use of lazy evaluation of carry bits, elimination of data-dependent branches and use of even cache accesses for all memory references.

摘要翻译： 提供了一种用于执行防止基于高速缓存和基于分支的攻击的模块化降级的时不变方法和装置。 模块化还原技术不会增加性能损失，并且具有侧向通道阻抗。 通过使用进位位的惰性评估，消除数据相关分支以及对所有存储器引用使用甚至高速缓存访​​问来提供侧向通道电阻。

公开(公告)号：US20100161536A1

公开(公告)日：2010-06-24

申请号：US12340360

申请日：2008-12-19

申请人： Christopher F. Clark ,  Vinodh Gopal ,  Gilbert M. Wolrich

发明人： Christopher F. Clark ,  Vinodh Gopal ,  Gilbert M. Wolrich

IPC分类号： G06N5/02

CPC分类号： H04L63/1416 ,  G06F21/552

摘要： A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.

摘要翻译： 提供了执行模式匹配的方法和装置。 该装置包括第一存储器，用于存储表示第一组模式组件的数据，以及第二存储器，用于存储表示第二组模式组件的数据，每个模式组件对应于第一组模式组件的一个或多个组件。 第一模式匹配器被配置为在输入流中检测一个或多个模式的第一分量，并且生成指示第一分量的检测的信号。 第二模式匹配器被配置为从第一模式匹配器接收信号并且检测该模式集合中的一个或多个模式的第二分量是否紧跟在输入流中的第一分量之后。

公开(公告)号：US20190236022A1

公开(公告)日：2019-08-01

申请号：US16377230

申请日：2019-04-07

申请人： Vinodh Gopal ,  Wajdi Feghali ,  Raghunandan Makaram

发明人： Vinodh Gopal ,  Wajdi Feghali ,  Raghunandan Makaram

IPC分类号： G06F12/109 ,  G06F3/06

CPC分类号： G06F12/109 ,  G06F3/0622 ,  G06F3/0659 ,  G06F3/0673

摘要： Methods and apparatus for ultra-secure accelerators. New ISA enqueue (ENQ) instructions with a wrapping key (WK) are provided to facilitate secure access to on-chip and off-chip accelerators in computer platforms and systems. The ISA ENQ with WK instructions include a dest operand having an address of an accelerator portal and a scr operand having the address of a request descriptor in system memory defining a job to be performed by an accelerator and including a wrapped key. Execution of the instruction writes a record including the src and a WK to the portal, and the record is enqueued in an accelerator queue if a slot is available. The accelerator reads the enqueued request descriptor and uses the WK to unwrap the wrapped key, which is then used to decrypt encrypted data read from one or more buffers in memory. The accelerator then performs one or more functions on the decrypted data as defined by the job and writes the output of the processing back to memory with optional encryption.

公开(公告)号：US20190042496A1

公开(公告)日：2019-02-07

申请号：US16140472

申请日：2018-09-24

申请人： Simon N. Peffers ,  Kirk S. Yap ,  Sean Gulley ,  Vinodh Gopal ,  Wajdi Feghali

发明人： Simon N. Peffers ,  Kirk S. Yap ,  Sean Gulley ,  Vinodh Gopal ,  Wajdi Feghali

IPC分类号： G06F13/16 ,  H04L29/06 ,  G06F13/28 ,  G06F13/40

摘要： Apparatus, systems and methods for implementing delayed decompression schemes. As a burst of packets comprising compressed packets and uncompressed packets are received over an interconnect link, they are buffered in a receive buffer without decompression. Subsequently, the packets are forwarded from the receive buffer to a consumer such as processor core, with the compressed packets being decompressed prior to reaching the processor core. Under a first delayed decompression approach, packets are decompressed when they are read from the receive buffer in conjunction with forwarding the uncompressed packet (or uncompressed data contained therein) to the consumer. Under a second delayed decompression scheme, the packets are read from the receive buffer and forwarded to a decompressor using a first datapath width matching the width of the packets, decompressed, and then forwarded to the consumer using a second datapath width matching the width of the uncompressed data.

公开(公告)号：US20160191238A1

公开(公告)日：2016-06-30

申请号：US14582707

申请日：2014-12-24

申请人： Kirk YAP ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

发明人： Kirk YAP ,  Gilbert Wolrich ,  Sudhir Satpathy ,  Sean Gulley ,  Vinodh Gopal ,  Sanu Mathew ,  Wajdi Feghali

IPC分类号： H04L9/08

CPC分类号： H04L9/0822 ,  G09C1/00 ,  H04L9/0631 ,  H04L2209/122

摘要： Embodiments of an invention for SMS4 acceleration hardware are disclosed. In an embodiment, an apparatus includes SMS4 hardware and key transformation hardware. The SMS4 hardware is to execute a round of encryption and a round of key expansion. The key transformation hardware is to transform a key to provide for the SMS4 hardware to execute a round of decryption.

摘要翻译： 公开了用于SMS4加速硬件的发明的实施例。 在一个实施例中，一种装置包括SMS4硬件和密钥变换硬件。 SMS4硬件是执行一轮加密和一轮关键扩展。 密钥转换硬件是转换密钥以提供SMS4硬件来执行一轮解密。

公开(公告)号：US08312363B2

公开(公告)日：2012-11-13

申请号：US12336029

申请日：2008-12-16

申请人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

发明人： Vinodh Gopal ,  Erdinc Ozturk ,  Gilbert Wolrich ,  Wajdi Feghali

IPC分类号： G06F11/00

CPC分类号： G06F7/724 ,  H03M13/091

摘要： In one embodiment, circuitry is provided to generate a residue based at least in part upon operations and a data stream generated based at least in part upon a packet. The operations may include at least one iteration of at least one reduction operation including (a) multiplying a first value with at least one portion of the data stream, and (b) producing a reduction by adding at least one other portion of the data stream to a result of the multiplying. The operations may include at least one other reduction operation including (c) producing another result by multiplying with a second value at least one portion of another stream based at least in part upon the reduction, (d) producing a third value by adding at least one other portion of the another stream to the another result, and (e) producing the residue by performing a Barrett reduction based at least in part upon the third value.

摘要翻译： 在一个实施例中，提供电路以至少部分地基于至少部分地基于分组产生的操作和数据流来生成残差。 操作可以包括至少一个缩减操作的迭代，包括（a）将第一值与数据流的至少一部分相乘，以及（b）通过添加数据流的至少一个其他部分来产生减少 是乘法的结果。 所述操作可以包括至少一个其它减少操作，其包括（c）至少部分地基于所述减少，通过与另一个流的至少一部分乘以第二值来产生另一结果，（d）通过至少加入来产生第三值 另一个流的另一部分到另一个结果，以及（e）至少部分地基于第三个值执行巴雷特还原来产生残留物。

公开(公告)号：US20100141488A1

公开(公告)日：2010-06-10

申请号：US12332083

申请日：2008-12-10

申请人： Selcuk Baktir ,  Vinodh Gopal ,  Gilbert Wolrich ,  Prashant Paliwal ,  Wajdi Feghali

发明人： Selcuk Baktir ,  Vinodh Gopal ,  Gilbert Wolrich ,  Prashant Paliwal ,  Wajdi Feghali

IPC分类号： H03M7/40

CPC分类号： H03M7/40 ,  H03M7/425

摘要： Techniques for decompressing a compressed input by determining, according to an ordering of allowable codewords, an offset for a variable length codeword detected in the input; accessing a record at the determined offset in a data structure having one record for each of the allowable codewords, each record including a portion for at least one of a literal value and a length value and a portion for a type value indicative of whether the record is for a literal or a length; and determining a decompressed output based at least in part on the accessed record.

摘要翻译： 用于通过根据允许的码字的排序确定在输入中检测到的可变长度码字的偏移来解压缩压缩输入的技术; 在具有每个可允许代码字的一个记录的数据结构中以确定的偏移量访问记录，每个记录包括用于文字值和长度值中的至少一个的部分，以及指示记录的类型值的部分 是一个字面或长度; 以及至少部分地基于所访问的记录来确定解压缩的输出。