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    Centerplaneless computer system
    51.
    发明授权
    Centerplaneless computer system 有权
    无中心计算机系统

    公开(公告)号：US07296106B2

    公开(公告)日：2007-11-13

    申请号：US10184474

    申请日：2002-06-28

    申请人： Drew G. Doblar ,  Robert E. Cypher

    发明人： Drew G. Doblar ,  Robert E. Cypher

    IPC分类号： G06F13/00 ,  G06F11/00 ,  G06F7/02 ,  G06F13/14 ,  H05K7/10 ,  H03M13/00

    CPC分类号： G06F13/4022

    摘要： A computer system which may allow a centerplaneless design. The computer system may include various client circuit boards including processor circuit boards, memory circuit boards and switch circuit boards. The processor circuit boards may each include at least one processor, while the memory circuit boards may each include memory which is accessible by each processor. The switch circuit boards may include a plurality of detachable connectors for interconnecting each of the processor circuit boards to each of the memory circuit boards. At least one of the switch circuit boards may convey redundant memory access information. Each of the boards may be hot swappable.

    摘要翻译： 可以允许中心分布式设计的计算机系统。 计算机系统可以包括各种客户端电路板，包括处理器电路板，存储器电路板和开关电路板。 处理器电路板可以各自包括至少一个处理器，而存储器电路板可以各自包括可由每个处理器访问的存储器。 开关电路板可以包括多个可拆卸连接器，用于将每个处理器电路板互连到每个存储器电路板。 至少一个开关电路板可以传送冗余存储器访问信息。 每个板可以是热插拔的。

    Encoded clocks to distribute multiple clock signals to multiple devices in a computer system
    52.
    发明授权
    Encoded clocks to distribute multiple clock signals to multiple devices in a computer system 有权

    公开(公告)号：US07065170B2

    公开(公告)日：2006-06-20

    申请号：US10622049

    申请日：2003-07-17

    申请人： Drew G. Doblar

    发明人： Drew G. Doblar

    IPC分类号： H04L7/00

    CPC分类号： G06F1/10 ,  G06F1/06 ,  H03L7/06

    摘要： An apparatus and method for distributing multiple clock signals to multiple devices using an encoded clock signal is provided. A source clock signal can be encoded to result in an encoded system clock. The encoded system clock can be distributed to multiple devices in a computer system. The devices can decode the encoded system clock signal to generate a system clock signal and a global clock signal. The system clock signal and the global clock signal can then be distributed to their respective clock loads on each device. In certain embodiments, additional information, such as state information, can be encoded into the encoded system clock. A device can be configured to decode the additional information and can alter its state accordingly.

    Clock divider for analysis of all clock edges
    53.
    发明授权
    Clock divider for analysis of all clock edges 有权
    时钟分频器，用于分析所有时钟沿

    公开(公告)号：US06441656B1

    公开(公告)日：2002-08-27

    申请号：US09919033

    申请日：2001-07-31

    申请人： Gin S. Yee ,  Drew G. Doblar

    发明人： Gin S. Yee ,  Drew G. Doblar

    IPC分类号： H03K2100

    CPC分类号： G06F1/10 ,  G06F1/06 ,  H03K5/1506 ,  H03K5/15066 ,  H03K2005/00234 ,  H03K2005/00286

    摘要： A method for dividing a high frequency clock signal for analysis of all clock edges has been developed. The method includes receiving a high frequency clock signal and dividing it up into multiple phases that represent respective edges of the clock signal. The initial phases are generated by the divider with each subsequent phase lagging its preceding phase by one clock cycle. Additional subsequent phases are generated by inverting corresponding initial phases.

    摘要翻译： 已经开发了用于分割所有时钟边缘的高频时钟信号进行分析的方法。 该方法包括接收高频时钟信号并将其分成表示时钟信号的相应边缘的多个相位。 初始相位由分频器产生，每个后续相位滞后于其前一相位一个时钟周期。 通过反转相应的初始相位来产生附加的后续阶段。

    Power and area efficient SerDes transmitter
    54.
    发明授权
    Power and area efficient SerDes transmitter 有权
    电源和区域高效的SerDes变送器

    公开(公告)号：US08542764B2

    公开(公告)日：2013-09-24

    申请号：US12353717

    申请日：2009-01-14

    申请人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    发明人： Dong J. Yoon ,  Dawei Huang ,  Drew G. Doblar

    IPC分类号： H04L27/00

    CPC分类号： H03M9/00 ,  H03K3/00 ,  H03L7/0814

    摘要： A system and method include a SerDes transmitter comprising a digital block operating in a digital voltage domain. The digital block can be configured to receive a first group of bits of data in parallel and store history bits from another group of data. The SerDes transmitter can further comprise an analog block operating in an analog voltage domain. The analog block can be configured to receive the first group of bits of data from the digital block, receive the history bits from the digital block, generate a plurality of combinations of bits with one or more bits from the first group of bits and zero or more bits from the history bits, align each combination of bits to a phase of a multi-phase clock; and input each combination into an output driver.

    摘要翻译： 一种系统和方法包括一个SerDes发射机，其包括以数字电压域工作的数字模块。 数字块可以被配置为并行地接收数据的第一组数据并存储来自另一组数据的历史比特。 SerDes发射机还可以包括在模拟电压域中工作的模拟块。 模拟块可以被配置为从数字块接收第一组数据，从数字块接收历史比特，从第一比特组生成具有一个或多个比特的比特的多个组合， 来自历史比特的更多比特，将每个比特组合对齐到多相时钟的相位; 并将每个组合输入到输出驱动器中。

    Low jitter and high bandwidth clock data recovery
    56.
    发明授权
    Low jitter and high bandwidth clock data recovery 有权
    低抖动和高带宽时钟数据恢复

    公开(公告)号：US08249199B2

    公开(公告)日：2012-08-21

    申请号：US12342825

    申请日：2008-12-23

    申请人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

    发明人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

    IPC分类号： H04L27/06

    CPC分类号： H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

    摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

    摘要翻译： 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

    Mechanism for constructing an oversampled waveform for a set of signals received by a receiver
    57.
    发明授权
    Mechanism for constructing an oversampled waveform for a set of signals received by a receiver 有权
    用于为接收机接收的一组信号构造过采样波形的机制

    公开(公告)号：US08249188B2

    公开(公告)日：2012-08-21

    申请号：US13175589

    申请日：2011-07-01

    申请人： Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

    发明人： Deqiang Song ,  Dawei Huang ,  Drew G. Doblar ,  Michael Stephen Harwood ,  Nirmal C. Warke

    IPC分类号： H04L27/00

    CPC分类号： H04L25/068

    摘要： A mechanism is provided for constructing an oversampled waveform for a set of incoming signals received by a receiver. In one implementation, the oversampled waveform is constructed by way of cooperation between the receiver and a waveform construction mechanism (WCM). The receiver receives the incoming signals, samples a subset of the incoming signals at a time, stores the subsets of sample values into a set of registers, and subsequently provides the subsets of sample values to the WCM. The WCM in turn sorts through the subsets of sample values, organizes them into proper orders, and “stitches” them together to construct the oversampled waveform for the set of incoming signals. With proper cooperation between the receiver and the WCM, and with proper processing logic on the WCM, it is possible to construct the oversampled waveform for the incoming signals without requiring large amounts of resources on the receiver.

    摘要翻译： 提供了一种用于为接收机接收的一组输入信号构造过采样波形的机制。 在一个实现中，过采样波形通过接收器和波形构造机构（WCM）之间的协作来构造。 接收机接收输入信号，一次对入局信号的子集进行采样，将样本值的子集存储到一组寄存器中，随后将样本值的子集提供给WCM。 WCM依次对样本值的子集进行排序，将它们组织成正确的顺序，并将它们“缝合”在一起，以构成输入信号集合的过采样波形。 通过接收机和WCM之间的适当协作，并且在WCM上具有适当的处理逻辑，可以为输入信号构造过采样波形，而不需要接收机上的大量资源。

    Use of emphasis to equalize high speed signal quality
    58.
    发明授权
    Use of emphasis to equalize high speed signal quality 有权
    使用重点来平衡高速信号质量

    公开(公告)号：US08229048B2

    公开(公告)日：2012-07-24

    申请号：US12208898

    申请日：2008-09-11

    申请人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

    发明人： Gabriel C. Risk ,  Drew G. Doblar ,  Pruthvi A. Chaudhari

    IPC分类号： H04B1/10

    CPC分类号： H04L25/03012

    摘要： A method, apparatus, and system for minimizing ringing in a high speed channel between a transmitter and a receiver in a circuit, including a component for initializing an n-tap equalization filter. The n-tap equalization filter includes numerous taps, each associated with each of numerous jitter pulses received from the transmitter at the receiver and over the channel. Many of the jitter pulses are greater than two. Further, each tap occurs at a time-domain point related to a time of a corresponding jitter pulse included within the numerous jitter pulses. Moreover, a component for applying the n-tap equalization filter to a subsequent signal sent over the channel is also included.

    摘要翻译： 一种用于最小化电路中的发射机和接收机之间的高速信道中的振铃的方法，装置和系统，包括用于初始化n抽头均衡滤波器的组件。 n抽头均衡滤波器包括多个抽头，每个抽头与接收器处的发射机和信道上的多个抖动脉冲中的每一个相关联。 许多抖动脉冲大于2。 此外，每个抽头发生在与包括在许多抖动脉冲内的相应抖动脉冲的时间相关的时域点。 此外，还包括用于将n抽头均衡滤波器应用于通过信道发送的后续信号的分量。

    ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRANSCEIVERS
    59.
    发明申请
    ASYMMETRIC DECISION FEEDBACK EQUALIZATION SLICING IN HIGH SPEED TRANSCEIVERS 有权
    高速收发器中的不对称决策反馈均衡切换

    公开(公告)号：US20110103458A1

    公开(公告)日：2011-05-05

    申请号：US12612449

    申请日：2009-11-04

    申请人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

    发明人： Dawei Huang ,  Deqiang Song ,  Jianghui Su ,  Drew G. Doblar

    IPC分类号： H04L27/01 ,  H04L27/00 ,  H03K5/153

    CPC分类号： H04L25/03878 ,  H04L25/03146

    摘要： An asymmetric DFE receiver circuit. The receiver circuit includes a voltage measuring unit configured to determine a signal voltage of a received signal, and a comparator unit configured to calculate a difference between the signal voltage and an evaluation threshold voltage and to compare the difference to the value of a midpoint voltage. The comparator unit is configured to generate a first control signal if the difference is greater than the midpoint voltage value or a second control signal if the signal voltage is less than the midpoint voltage value. The receiver includes an adjustment circuit configured to adjust the evaluation threshold voltage toward the signal voltage if the first control signal is generated and away from the signal voltage if the second control signal is generated. The rates of adjustment may vary depending upon whether the received signal is a transition bit or a non-transition bit.

    摘要翻译： 不对称DFE接收器电路。 接收器电路包括：电压测量单元，被配置为确定接收信号的信号电压;以及比较器单元，被配置为计算信号电压和评估阈值电压之间的差，并将该差与中点电压的值进行比较。 比较器单元被配置为如果差值大于中点电压值则产生第一控制信号，或者如果信号电压小于中点电压值则产生第二控制信号。 所述接收机包括：调整电路，被配置为如果产生所述第一控制信号并且如果产生所述第二控制信号则将所述评估阈值电压调整到所述信号电压。 调整速率可以根据接收到的信号是转换位还是非转换位而变化。