公开(公告)号：US08543848B2

公开(公告)日：2013-09-24

申请号：US12886711

申请日：2010-09-21

申请人： Michael Bushue ,  Drew G. Doblar

发明人： Michael Bushue ,  Drew G. Doblar

IPC分类号： G06F1/26 ,  G06F1/32

CPC分类号： H02M1/36 ,  H02J9/005

摘要： A method for reducing latency using a charging module when activating a power supply unit (PSU) among a plurality of PSUs in a power supply system. The method includes: Receiving, by the PSU from a power input feed, input power; receiving, from a supply bus shared by the plurality of PSUs, a first controlled signal designating a status of the PSU as standby; disabling, in response to the first controlled signal, a switching regulator of the PSU; receiving, from a voltage rail of the supply bus, charge flowing through a resistor of the charging module to maintain a charge of an output capacitor of the switching regulator; receiving a second controlled signal designating the status of the PSU as active; enabling the switching regulator; outputting a voltage from the PSU through the charging module to the voltage rail; and charging the output capacitor using the PSU.

摘要翻译： 一种当在电源系统中的多个PSU中激活电源单元（PSU）时，使用充电模块来减少等待时间的方法。 该方法包括：通过PSU从电源输入馈线接收输入电源; 从所述多个PSU共享的供电总线接收将所述PSU的状态指定为待机的第一受控信号; 响应于第一受控信号，禁用PSU的开关调节器; 从所述电源总线的电压轨道接收流过所述充电模块的电阻器的电荷，以维持所述开关调节器的输出电容器的电荷; 接收指定PSU状态为活动的第二受控信号; 启用开关稳压器; 将来自PSU的电压通过充电模块输出到电压轨; 并使用PSU对输出电容器充电。

公开(公告)号：US20120072754A1

公开(公告)日：2012-03-22

申请号：US12886843

申请日：2010-09-21

申请人： Drew G. Doblar ,  Michael Bushue

发明人： Drew G. Doblar ,  Michael Bushue

IPC分类号： G06F11/30 ,  G06F1/26

CPC分类号： G06F11/3062 ,  G06F1/3206 ,  G06F11/3051 ,  G06F11/3082

摘要： A non-transitory computer readable storage medium having computer readable program code embodied therein, where the computer readable program code is adapted to, when executed by a processor, implement a method for managing a power supply system. The method includes identifying a number of power supplies included in the power supply system, and determining a first system mode for the power supply system. The method also includes determining a first operating order for the power supplies, and assigning a first ACTIVE ON threshold to each of the power supplies to obtain a number of first ACTIVE ON thresholds. The method further includes assigning a first ACTIVE STANDBY OFF threshold to each of the power supplies to obtain a number of first ACTIVE STANDBY OFF thresholds, where the power supply system provides electrical power to at least one computer system.

摘要翻译： 一种具有体现在其中的计算机可读程序代码的非瞬时计算机可读存储介质，其中计算机可读程序代码在由处理器执行时实施用于管理电源系统的方法。 该方法包括识别包括在电源系统中的多个电源，以及确定供电系统的第一系统模式。 该方法还包括确定电源的第一操作顺序，以及为每个电源分配第一ACTIVE ON阈值以获得多个第一ACTIVE ON阈值。 该方法还包括为每个电源分配第一ACTIVE STANDBY OFF阈值以获得多个第一ACTIVE STANDBY OFF阈值，其中电源系统向至少一个计算机系统提供电力。

公开(公告)号：US20120072738A1

公开(公告)日：2012-03-22

申请号：US12886711

申请日：2010-09-21

申请人： Michael Bushue ,  Drew G. Doblar

发明人： Michael Bushue ,  Drew G. Doblar

IPC分类号： G06F1/26

CPC分类号： H02M1/36 ,  H02J9/005

摘要： A method for reducing latency using a charging module when activating a power supply unit (PSU) among a plurality of PSUs in a power supply system. The method includes: Receiving, by the PSU from a power input feed, input power; receiving, from a supply bus shared by the plurality of PSUs, a first controlled signal designating a status of the PSU as standby; disabling, in response to the first controlled signal, a switching regulator of the PSU; receiving, from a voltage rail of the supply bus, charge flowing through a resistor of the charging module to maintain a charge of an output capacitor of the switching regulator; receiving a second controlled signal designating the status of the PSU as active; enabling the switching regulator; outputting a voltage from the PSU through the charging module to the voltage rail; and charging the output capacitor using the PSU.

摘要翻译： 一种当在电源系统中的多个PSU中激活电源单元（PSU）时，使用充电模块来减少等待时间的方法。 该方法包括：通过PSU从电源输入馈线接收输入电源; 从所述多个PSU共享的供电总线接收将所述PSU的状态指定为待机的第一受控信号; 响应于第一受控信号，禁用PSU的开关调节器; 从所述电源总线的电压轨道接收流过所述充电模块的电阻器的电荷，以维持所述开关调节器的输出电容器的电荷; 接收指定PSU状态为活动的第二受控信号; 启用开关稳压器; 将来自PSU的电压通过充电模块输出到电压轨; 并使用PSU对输出电容器充电。

公开(公告)号：US08014159B2

公开(公告)日：2011-09-06

申请号：US12429915

申请日：2009-04-24

申请人： Drew G. Doblar ,  Gurpreet S. Dayal

发明人： Drew G. Doblar ,  Gurpreet S. Dayal

IPC分类号： H05K5/00

CPC分类号： H05K7/1454 ,  H05K1/0271 ,  H05K3/366 ,  H05K2201/044 ,  H05K2201/10189 ,  H05K2201/10303 ,  H05K2201/10409 ,  H05K2201/10545 ,  H05K2201/2009 ,  H05K2203/167

摘要： A mounting plane assembly (e.g., backplane or midplane) is provided for interconnecting a plurality of daughterboards in a server computer. The mounting plane assembly includes a printed circuit board (“PCB”) that has a plurality of shared mounting holes for attaching connector alignment pins to a front side of the PCB as well as mechanical support elements to a back side of the PCB through the same mounting holes.

摘要翻译： 提供了一种安装平面组件（例如背板或中平面），用于互连服务器计算机中的多个子板。 安装平面组件包括印刷电路板（“PCB”），该印刷电路板具有多个共用的安装孔，用于将连接器对准销连接到PCB的正面以及通过其连接到PCB背面的机械支撑元件 安装孔。

公开(公告)号：US20100158182A1

公开(公告)日：2010-06-24

申请号：US12343426

申请日：2008-12-23

申请人： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

发明人： Drew G. Doblar ,  Dawei Huang ,  Deqiang Song

IPC分类号： H03D3/24

CPC分类号： H04L7/0008 ,  G06F1/10 ,  H04L25/061

摘要： A method and apparatus for reducing the amplification of the duty cycle distortion of high frequency clock signals when is provided. A data signal is sent to a receiver via a first channel. A clock signal is sent to the receiver via a second channel. The clock signal is filtered to substantially remove therefrom low frequency components before the clock signal is used by the receiver to recover data from the data signal.

摘要翻译： 提供一种用于降低高频时钟信号的占空比失真的放大的方法和装置。 数据信号通过第一通道发送到接收器。 时钟信号通过第二通道发送到接收器。 在时钟信号被接收机使用以从数据信号恢复数据之前，时钟信号被滤波以基本上从其中去除低频分量。

公开(公告)号：US20100158177A1

公开(公告)日：2010-06-24

申请号：US12342825

申请日：2008-12-23

申请人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

发明人： Drew G. Doblar ,  Dawei Huang ,  Gabriel C. Risk

IPC分类号： H04L7/00

CPC分类号： H04L7/0062 ,  H04L7/0334 ,  H04L7/0337 ,  H04L7/10

摘要： A method of implementing a low jitter and high bandwidth clock and data recovery (CDR) apparatus includes acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjusting a recovered clock phase based on the accumulated votes. A computer readable medium storing instructions to implement a low jitter and high bandwidth CDR apparatus, the instructions includes functionality to: acquiring early, optimal, and late votes; determining which votes are allowed and weighted; disallowing votes not determined to as allowed; weighing votes, wherein votes that would make the CDR move to an extreme of a zero crossing are weighted less; and accumulating votes and adjust recovered clock phase.

摘要翻译： 实现低抖动和高带宽时钟和数据恢复（CDR）装置的方法包括获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 根据累计投票累积投票数，调整恢复时钟阶段。 一种存储用于实现低抖动和高带宽CDR装置的指令的计算机可读介质，所述指令包括以下功能：获取早期，最佳和晚期投票; 确定哪些投票是允许和加权的; 不允许票决定为允许; 称投票，其中使CDR移动到零交叉极端的投票被加权较少; 累积投票并调整恢复时钟阶段。

公开(公告)号：US07409491B2

公开(公告)日：2008-08-05

申请号：US11302728

申请日：2005-12-14

申请人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao R. Wu

发明人： Drew G. Doblar ,  Gabriel C. Risk ,  Chung-Hsiao R. Wu

IPC分类号： G06F13/14

CPC分类号： G06F13/1684 ,  G11C5/00

摘要： A memory system comprising memory modules including memory chips stacked with switching circuits. A memory controller coupled to the memory modules is configured to initiate memory accesses. When a stacked switching circuit detects the memory access, the switching circuit routes the access to another memory module if the access is not directed to a memory chip of the receiving memory module, or processes the access locally if the access is directed to a memory chip of the receiving memory module. The memory controller and memory modules are coupled via bi-directional serial links. Each memory module may include multiple stacked switching circuits, each of which may be coupled to fewer than all of the memory chips within the memory module. Switching circuits further include circuitry configured to de-serialize data prior to conveyance to a memory chip, and serialize data received from a DRAM chip prior to transmitting the received data. Switching circuits may be coupled to a stacked memory chip via a flexible interconnect, and may also be manufactured side by side with a corresponding memory chip on a flexible circuit board.

摘要翻译： 一种包括存储器模块的存储器系统，包括堆叠有开关电路的存储器芯片。 耦合到存储器模块的存储器控​​制器被配置为启动存储器访问。 当堆叠的开关电路检测到存储器访问时，如果访问不被引导到接收存储器模块的存储器芯片，则切换电路将访问路由到另一个存储器模块，或者如果访问被定向到存储器芯片则在本地处理访问 的接收存储器模块。 存储器控制器和存储器模块通过双向串行链路耦合。 每个存储器模块可以包括多个堆叠的开关电路，每个存储器模块可以耦合到比存储器模块内的所有存储器芯片少。 开关电路还包括被配置为在传送到存储器芯片之前对数据进行反序列化的电路，以及在发送所接收的数据之前串行从DRAM芯片接收的数据。 开关电路可以通过柔性互连耦合到堆叠的存储器芯片，并且还可以与柔性电路板上的对应的存储器芯片并排地制造。

公开(公告)号：US07224638B1

公开(公告)日：2007-05-29

申请号：US11304166

申请日：2005-12-15

申请人： Gabriel C. Risk ,  Leandro A. Chua, Jr. ,  Drew G. Doblar

发明人： Gabriel C. Risk ,  Leandro A. Chua, Jr. ,  Drew G. Doblar

IPC分类号： G11C8/00

CPC分类号： G11C7/20 ,  G11C7/22 ,  G11C7/222

摘要： A data communications system is disclosed. The data communications system comprises two clock domains. A first clock domain includes a transmitter and a first clock signal. A second clock domain includes a receiver and a second clock signal. The transmitter conveys the first clock signal and a data signal to the receiver. The receiver: (a) counts a first number of transitions of the second clock signal in response to detecting a transition of the first clock signal; (b) maintains a first count of the number of transitions of the second clock signal; (c) samples the data signal and maintains a second count of the number of transitions of the second clock signal in response to detecting the first count equals a first pre-determined value; and (d) samples the data signal and resets the second count in response to detecting the second count equals a second pre-determined value.

摘要翻译： 公开了一种数据通信系统。 数据通信系统包括两个时钟域。 第一时钟域包括发射机和第一时钟信号。 第二时钟域包括接收机和第二时钟信号。 发射机将第一时钟信号和数据信号传送到接收机。 接收机：（a）响应于检测到第一时钟信号的转变，对第二时钟信号的第一数量的转换进行计数; （b）维持第二时钟信号的转换次数的第一计数; （c）对所述数据信号进行采样，并响应于检测到所述第一计数等于第一预定值而维持所述第二时钟信号的转换次数的第二计数; 以及（d）对数据信号进行采样，并且响应于检测到第二计数等于第二预定值而复位第二计数。

公开(公告)号：US07139308B2

公开(公告)日：2006-11-21

申请号：US10117427

申请日：2002-04-05

申请人： Drew G. Doblar ,  Jyh-Ming Jong ,  Brian L. Smith ,  Jurgen Schulz

发明人： Drew G. Doblar ,  Jyh-Ming Jong ,  Brian L. Smith ,  Jurgen Schulz

IPC分类号： H04L25/60

CPC分类号： H04L7/0008 ,  H04L7/0045

摘要： A device configured to recover and repeat source synchronous data. In one embodiment, the device is configured to receive source synchronous data via a first interface, recover the received data utilizing a corresponding received source synchronous clock signal, and transmit the recovered data and a corresponding clock signal in a source synchronous manner. In one embodiment, the device is configured to operate as a repeater without benefit of an internal clock signal. In addition, the device may be configured to remove data jitter and renew or restore amplitude to attenuated signals prior to retransmission.

公开(公告)号：US06516422B1

公开(公告)日：2003-02-04

申请号：US09320794

申请日：1999-05-27

申请人： Drew G. Doblar ,  Leo Yuan ,  Emrys J. Williams

发明人： Drew G. Doblar ,  Leo Yuan ,  Emrys J. Williams

IPC分类号： G06F1100

CPC分类号： G06F11/1604 ,  G06F1/04 ,  G06F11/20

摘要： A system and method for providing redundant, synchronized clocks in a computer system. Upon a failure of a master clock signal, the system switches over to a slave clock signal synchronized with the master clock signal. Switching logic is coupled to receive a first clock signal and a second clock signal. The switching logic selects either the first clock signal or the second clock signal as a local clock signal. The switching logic further monitors the first clock signal for a failure. If a failure is monitored, the switching logic accepts the second clock signal as the local clock signal in place of the first clock signal. One or more clock local loads operate according to the local clock signal. The switching logic may control the input to a phase locked loop (PLL) that provides the local clock signal to the local clock loads. The method includes a PLL synchronizing an output clock signal with the master clock signal. The output clock signal is used by at least one local clock load for timing. The switching logic monitors the master clock signal and the slave clock signal for a failure. Upon a failure of either the master clock signal or the slave clock signal, the switching logic notifies a system controller of the failure. Upon the failure of the first clock signal, the switching logic switches the second clock signal in place of the first clock signal as the master clock signal for the PLL, causes the second clock signal to fail-over and to take over as the master clock source to the PLL, and causes the second clock source to provide a reference control signal to the second clock source. Clock switching is automatic and does not interrupt or interfere with operation of the computer system.

摘要翻译： 一种用于在计算机系统中提供冗余的同步时钟的系统和方法。 在主时钟信号故障时，系统切换到与主时钟信号同步的从时钟信号。 开关逻辑被耦合以接收第一时钟信号和第二时钟信号。 开关逻辑选择第一时钟信号或第二时钟信号作为本地时钟信号。 开关逻辑进一步监视第一时钟信号以进行故障。 如果监视故障，则开关逻辑代替第一个时钟信号接收第二个时钟信号作为本地时钟信号。 一个或多个时钟本地负载根据本地时钟信号工作。 开关逻辑可以将输入控制到将本地时钟信号提供给本地时钟负载的锁相环（PLL）。 该方法包括使输出时钟信号与主时钟信号同步的PLL。 输出时钟信号由至少一个本地时钟负载用于定时。 开关逻辑监视主时钟信号和从时钟信号以进行故障。 在主时钟信号或从时钟信号失效时，开关逻辑通知系统控制器故障。 当第一时钟信号失效时，开关逻辑将第二时钟信号替换为第一时钟信号，作为PLL的主时钟信号，使第二时钟信号故障切换并接管作为主时钟 源，并使第二时钟源向第二时钟源提供参考控制信号。 时钟切换是自动的，不会中断或干扰计算机系统的操作。