中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

72 records (took 0.015 seconds)

    N-alkylation of heterocyclic, aromatic amines
    52.
    发明授权
    N-alkylation of heterocyclic, aromatic amines 失效
    杂环芳族胺的N-烷基化

    公开(公告)号：US5283341A

    公开(公告)日：1994-02-01

    申请号：US880587

    申请日：1992-05-08

    Applicant: Norio Tanaka ,  Masataka Hatanaka ,  Yoshihisa Watanabe

    Inventor： Norio Tanaka ,  Masataka Hatanaka ,  Yoshihisa Watanabe

    IPC: B01J27/13 ,  B01J31/24 ,  C07B61/00 ,  C07D231/12 ,  C07D231/20 ,  C07D231/22 ,  C07D231/38 ,  C07D233/54 ,  C07D233/58 ,  C07D249/04 ,  C07D249/06 ,  C07D249/08 ,  C07D249/18 ,  C07D249/20 ,  B01J23/46 ,  C07D249/22 ,  C07D403/02

    CPC classification number: C07D231/12

    Abstract: A process for producing a heterocyclic tertiary amine of the formula (III): ##STR1## wherein A is a nitrogen atom or C-R.sup.5, B is a nitrogen atom or C-R.sup.6, is a single bond or a double bond, and each of R.sup.1, R.sup.2, R.sup.3, R.sup.4, R.sup.5 and R.sup.6 which may be the same or different, is a hydrogen atom, an acyl group, a halogen atom, a cyano group, etc., provided that two of R.sup.1, R.sup.2, R.sup.3 and R.sup.4 may together form a 3-membered, 4-membered, 5-membered or 6-membered aliphatic ring, a heterocyclic rig or aromatic ring, and R.sup.7 is a C.sub.1-6 alkyl group which may be substituted, etc., which process comprises reacting a heterocyclic secondary amine of the formula (I): ##STR2## wherein A, B, , R.sup.1, R.sup.2, R.sup.3 and R.sup.4 are as defined above, with an alkylating agent of the formula (II):R.sup.7 --X (II)wherein R.sup.7 is as defined above, and X is a hydroxyl group, a halogen atom, a OSO.sub.3 R.sup.7 group, a OSO.sub.2 R.sup.7 group, a OCO.sub.2 R.sup.7 group, a OCOR.sup.7 group, a OP(O)(OR.sup.7) group, a OP(O)O(R.sup.7).sub.2 group or an amino group, in the presence of a catalyst of Group VIII of the Periodic Table.

    Abstract translation: 制备式（III）的杂环叔胺的方法：（*化学结构*）（III）其中A为氮原子或C-R5，B为氮原子或C-R6，为单键或 双键，R 1，R 2，R 3，R 4，R 5和R 6可以相同或不同，为氢原子，酰基，卤素原子，氰基等，条件是两个 R 1，R 2，R 3和R 4可以一起形成3元，4元，5元或6元脂族环，杂环基或芳环，并且R 7为可被取代的C 1-6烷基， 等等，该方法包括使式（I）的杂环仲胺：其中A，B，，R 1，R 2，R 3和R 4如上所定义的式（I）化合物与 式（II）：其中R7如上定义的R7-X（II），X是羟基，卤素原子，OSO3R7基，OSO2R7基，OCO2R7基，OCOR7基，OP（O ）（OR 7）基，OP（O）O（R 7）2基或氨基， n元素周期表第VIII族催化剂的存在。

    Electrolytic treatment of waste water
    54.
    发明授权
    Electrolytic treatment of waste water 失效
    废水电解处理

    公开(公告)号：US4014766A

    公开(公告)日：1977-03-29

    申请号：US625099

    申请日：1975-10-23

    Applicant: Yoshihisa Watanabe ,  Naohiro Nojiri

    Inventor： Yoshihisa Watanabe ,  Naohiro Nojiri

    IPC: C02F1/461 ,  C02F1/463 ,  C02F1/48 ,  C02F1/72 ,  C02C5/12 ,  C25C1/10

    CPC classification number: C02F1/488 ,  C02F1/46114 ,  C02F1/463 ,  C02F1/72 ,  C02F2101/22

    Abstract: Waste water is subjected to electrolysis in an electrolytic cell having an anode comprising an insoluble central electrode and a body of particulate iron pieces disposed therearound and in electrical contact therewith, whereby impurities in the waste water become occluded within a floc of iron hydroxide formed by electrolytic dissolution of the iron pieces, and the floc containing the impurities is subjected to oxidation processing and is thereafter separated. A magnetic field can be applied to the waste water thus treated thereby to promote sedimentation of the floc.

    Abstract translation: 废水在具有阳极的电解槽中进行电解，该阳极包含不溶性中心电极和设置在其周围并与其电接触的颗粒状铁屑体，由此废水中的杂质被吸收在由电解质形成的氢氧化铁絮凝物中 将铁片和含有杂质的絮状体的溶解进行氧化处理，然后分离。 可以对这样处理的废水施加磁场，从而促进絮凝物的沉降。

    Semiconductor device
    57.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08791517B2

    公开(公告)日：2014-07-29

    申请号：US13052152

    申请日：2011-03-21

    Applicant: Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

    Inventor： Hiroyuki Kutsukake ,  Yoshiko Kato ,  Yoshihisa Watanabe ,  Koichi Fukuda ,  Kazunori Masuda

    IPC: H01L29/78 ,  H01L29/92

    CPC classification number: H01L27/11526 ,  H01L27/11521 ,  H01L27/11529

    Abstract: According to one embodiment, a semiconductor device includes at least one semiconductor region provided in a semiconductor substrate, and a capacitor group including a plurality of capacitors provided in the semiconductor region, each capacitor including a capacitor insulating film provided on the semiconductor region, a capacitor electrode provided on the capacitor insulating film, and at least one diffusion layer provided in the semiconductor region adjacent to the capacitor electrode.

    Abstract translation: 根据一个实施例，半导体器件包括设置在半导体衬底中的至少一个半导体区域和包括设置在半导体区域中的多个电容器的电容器组，每个电容器包括设置在半导体区域上的电容器绝缘膜，电容器 设置在电容器绝缘膜上的电极以及设置在与电容器电极相邻的半导体区域中的至少一个扩散层。

    Nonvolatile semiconductor memory, method for reading out thereof, and memory card
    58.
    发明授权
    Nonvolatile semiconductor memory, method for reading out thereof, and memory card 失效

    公开(公告)号：US08243517B2

    公开(公告)日：2012-08-14

    申请号：US12730330

    申请日：2010-03-24

    Applicant: Makoto Iwai ,  Yoshihisa Watanabe

    Inventor： Makoto Iwai ,  Yoshihisa Watanabe

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

    Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

    Nonvolatile semiconductor memory, method for reading out thereof, and memory card
    59.
    发明授权
    Nonvolatile semiconductor memory, method for reading out thereof, and memory card 有权
    非易失性半导体存储器，读出方法和存储卡

    公开(公告)号：US08213232B2

    公开(公告)日：2012-07-03

    申请号：US13210431

    申请日：2011-08-16

    Applicant: Makoto Iwai ,  Yoshihisa Watanabe

    Inventor： Makoto Iwai ,  Yoshihisa Watanabe

    IPC: G11C16/04

    CPC classification number: G11C16/0483 ,  G11C11/5642 ,  G11C16/26

    Abstract: A nonvolatile semiconductor memory includes: a memory cell unit including a plurality of memory cells having an electric charge accumulation layer and a control electrode, said memory cells being electrically connected in series; a plurality of word lines, each of which is electrically connected to said control electrode of said plurality of memory cells; a source line electrically connected to said memory cells at one end of said memory cell unit; a bit line electrically connected to said memory cells at the other end of said memory cell unit; and a control signal generation circuit, which during a data readout operation staggers a timing for selecting the word line connected to said memory cells of said memory cell unit from a timing for selecting a non-selected word line connected to a non-selected memory.

    Abstract translation: 非易失性半导体存储器包括：存储单元单元，包括具有电荷累积层和控制电极的多个存储单元，所述存储单元串联电连接; 多个字线，其各自电连接到所述多个存储单元的所述控制电极; 在所述存储单元单元的一端电连接到所述存储单元的源极线; 在所述存储单元单元的另一端电连接到所述存储单元的位线; 以及控制信号生成电路，其在数据读出操作期间，从连接到未选择的存储器的未选择的字线的选择时刻开始，选择连接到所述存储单元的所述存储单元的字线的定时。

    NAND-type flash memory and NAND-type flash memory controlling method
    60.
    发明授权
    NAND-type flash memory and NAND-type flash memory controlling method 有权
    NAND型闪存和NAND型闪存控制方法

    公开(公告)号：US08199582B2

    公开(公告)日：2012-06-12

    申请号：US13043624

    申请日：2011-03-09

    Applicant: Yuka Furuta ,  Yoshihisa Watanabe

    Inventor： Yuka Furuta ,  Yoshihisa Watanabe

    IPC: G11C16/04

    CPC classification number: G11C16/26 ,  G11C16/0483

    Abstract: A method of controlling a NAND-type flash memory provided with a latch circuit in which data is temporarily stored has measuring a first consumption current of the latch circuit in a first state in which the latch circuit is caused to retain first logic; measuring a second consumption current of the latch circuit in a second state in which the latch circuit is caused to retain second logic obtained by inverting the first logic; and comparing the first consumption current and the second consumption current to cause the latch circuit to retain logic corresponding to the state corresponding to a smaller one of the first consumption current and the second consumption current.

    Abstract translation: 一种控制NAND型闪速存储器的方法，该闪存具有临时存储数据的锁存电路，在锁存电路被保留第一逻辑的第一状态下测量锁存电路的第一消耗电流; 在第二状态下测量锁存电路的第二消耗电流，其中使得所述锁存电路保持通过反转所述第一逻辑而获得的第二逻辑; 以及比较所述第一消耗电流和所述第二消耗电流以使所述锁存电路保持与所述第一消耗电流和所述第二消耗电流中的较小的一个相对应的状态。

Patent Agency Ranking