公开(公告)号：US08102715B2

公开(公告)日：2012-01-24

申请号：US13100947

申请日：2011-05-04

申请人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

发明人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

IPC分类号： G11C11/34

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/144 ,  G11C7/20 ,  G11C11/4072

摘要： Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

摘要翻译： 公开了装置，方法和系统，包括当偏置电压转变到地电位时，防止偏置电压升高到高于存储节点电压的电平的装置，方法和系统。 例如，可以使用第一电压发生器来产生偏置电压以偏置存储器阵列中的存储器单元中的晶体管。 可以利用第二电压发生器来产生板电压。 存储单元可以包括衬底上的晶体管和电容器。 电容器从晶体管的漏极连接到板电压。 存储节点电压位于晶体管的漏极处。 功率控制器可以向第一和第二电压发生器提供关闭信号。 偏压可以从小于零伏的电压转变到地。 偏置电压上升到接地的速率使得偏置电压保持在小于或等于转换时间段内的存储节点电压。

公开(公告)号：US20110302328A1

公开(公告)日：2011-12-08

申请号：US13213997

申请日：2011-08-19

申请人： Yutaka Ito ,  Tadashi Yamamoto

发明人： Yutaka Ito ,  Tadashi Yamamoto

IPC分类号： G06F3/00

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F3/0659

摘要： Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 公开了在存储器内操作以执行内部命令，在传送期间暂停命令的执行以及在传送周期之后执行外部命令的装置，系统和方法。 公开了附加装置，系统和方法。

公开(公告)号：US08014222B2

公开(公告)日：2011-09-06

申请号：US12795151

申请日：2010-06-07

申请人： Yutaka Ito ,  Masayoshi Nomura ,  Keiichiro Abe

发明人： Yutaka Ito ,  Masayoshi Nomura ,  Keiichiro Abe

IPC分类号： G11C7/00

CPC分类号： G11C8/18 ,  G11C7/1078 ,  G11C7/109 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4076 ,  G11C2207/2227 ,  G11C2211/4067

摘要： A memory device includes a command decoder and control interface logic. One or more external inputs, such as row and column address strobes, communicate with the command decoder through the control interface logic. A control signal is also in communication with the control interface logic. During operation of a drowsy mode in the memory device, a self-refresh signal causes the control signal to disable the external inputs. With the external inputs disabled, command hazards are reduced when exiting drowsy mode.

摘要翻译： 存储器件包括命令解码器和控制接口逻辑。 一个或多个外部输入，例如行和列地址选通，通过控制接口逻辑与命令解码器通信。 控制信号也与控制接口逻辑通信。 在存储器件中的困倦模式操作期间，自刷新信号使控制信号禁止外部输入。 当外部输入禁用时，退出困倦模式时，命令危害会降低。

公开(公告)号：US20110018426A1

公开(公告)日：2011-01-27

申请号：US12933335

申请日：2009-03-18

申请人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

发明人： Kenji Toda ,  Kazuyoshi Uematsu ,  Mineo Sato ,  Tetsu Umeda ,  Yutaka Ito

IPC分类号： H01J1/62 ,  C09K11/77

CPC分类号： C09K11/7792 ,  C09K11/0883 ,  H01J61/44 ,  H01L33/502

摘要： Provided are phosphors that can provide emission devices that can further improve emission characteristics, principally, color rendering. Disclosed are phosphors made by substituting at least a portion of M2 in compounds represented by Formula (1) with M4 (M4 represents a trivalent cationic element), substituting a portion of O in said compound with M5 (M5 represents a trivalent anionic element) and substituting a portion of M1 and/or M2 in said compound with an activated element. In Formula (1): aM1O.3M2O.6M3O2 (In Formula (1), M1 represents one or more alkaline-earth elements selected from a group comprising Ba, Sr and Ca, M2 represents one or more divalent metal elements selected from a group comprising Mg and Zn, M3 represents a tetravalent metal element and a is a value in the range 3 to 9.)

摘要翻译： 提供了可以提供能够进一步改善发射特性的发射器件的荧光体，主要是显色。 公开了通过用M4（M4代表三价阳离子元素）取代由式（1）表示的化合物中的至少一部分M2而制备的荧光体，用M5（M5表示三价阴离子元素）代替所述化合物中的一部分O， 用活化元素代替所述化合物中M1和/或M2的一部分。 式（1）中，aM1O3M2O6M3O2（式（1）中，M1表示一种以上选自Ba，Sr，Ca的碱土类元素，M2表示选自组中的一种以上的二价金属元素 包括Mg和Zn，M3表示四价金属元素，a是3至9的值）

公开(公告)号：US20100135065A1

公开(公告)日：2010-06-03

申请号：US12698808

申请日：2010-02-02

申请人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

发明人： Yutaka Ito ,  Adrian J. Drexler ,  Brandi M. Jones

IPC分类号： G11C11/24 ,  G11C5/14

CPC分类号： G11C11/4074 ,  G11C5/14 ,  G11C5/144 ,  G11C7/20 ,  G11C11/4072

摘要： Apparatus, methods, and systems are disclosed, including those that are to prevent a bias voltage from rising to a higher level than a storage node voltage as the bias voltage transitions to a ground level. For example a first voltage generator may be utilized to generate a bias voltage to bias a transistor in a memory cell in a memory array. A second voltage generator may be utilized to generate an plate voltage. The memory cell may include a transistor on a substrate and a capacitor. The capacitor connects from a drain of the transistor to the plate voltage. The storage node voltage is located at the drain of the transistor. A power controller may provide an off signal to the first and second voltage generators. The bias voltage may then transition to ground from a voltage less than zero volts. The rate of the bias voltage rise to ground is such that the bias voltage is maintained at less than or equal to the storage node voltage during the transition time period.

摘要翻译： 公开了装置，方法和系统，包括当偏置电压转变到地电位时，防止偏置电压升高到高于存储节点电压的电平的装置，方法和系统。 例如，可以使用第一电压发生器来产生偏置电压以偏置存储器阵列中的存储器单元中的晶体管。 可以利用第二电压发生器来产生板电压。 存储单元可以包括衬底上的晶体管和电容器。 电容器从晶体管的漏极连接到板电压。 存储节点电压位于晶体管的漏极处。 功率控制器可以向第一和第二电压发生器提供关闭信号。 偏压可以从小于零伏的电压转变到地。 偏置电压上升到接地的速率使得偏置电压保持在小于或等于转换时间段内的存储节点电压。

公开(公告)号：US07602397B2

公开(公告)日：2009-10-13

申请号：US11574666

申请日：2005-09-05

申请人： Takeshi Okubo ,  Yutaka Ito

发明人： Takeshi Okubo ,  Yutaka Ito

IPC分类号： G09G5/00

CPC分类号： A63F13/52 ,  A63F13/10 ,  A63F13/537 ,  A63F13/57 ,  A63F13/803 ,  A63F2300/303 ,  A63F2300/64 ,  A63F2300/8017 ,  G09B9/05

摘要： An operation input reception unit (201) receives an operation input for a virtual vehicle to be run on the running path. A running condition managing unit (203) manages the running condition of the virtual vehicle based on the received operation input. A load calculation unit (205) calculates a load imposed on a virtual operator in the virtual vehicle, based on the managed running condition. Meanwhile, a symbol drawing unit (401) draws a load symbol whose display position changes according to the calculated load. A tire image drawing unit (402) draws an image of a tire whose display manner changes according to the calculated load. A meter image creating unit (403) creates a meter image including the drawn load symbol and image of the tire. Then, a display control unit (207) displays the created meter image on a predetermined monitor.

摘要翻译： 操作输入接收单元（201）在运行路径上接收要运行的虚拟车辆的操作输入。 运行条件管理单元（203）基于接收到的操作输入来管理虚拟车辆的行驶状态。 负载计算单元（205）基于管理的运行条件来计算虚拟车辆中的虚拟操作者的负荷。 同时，符号描绘单元（401）根据所计算的负载绘制其显示位置改变的负载符号。 轮胎图像绘制单元（402）根据所计算的载荷绘制显示方式改变的轮胎的图像。 仪表图像创建单元（403）创建包括绘制的负载符号和轮胎的图像的仪表图像。 然后，显示控制单元（207）将所生成的测量图像显示在预定的监视器上。

公开(公告)号：US20090049455A1

公开(公告)日：2009-02-19

申请号：US11840074

申请日：2007-08-16

申请人： Yutaka Ito ,  Tadashi Yamamoto

发明人： Yutaka Ito ,  Tadashi Yamamoto

IPC分类号： G06F9/44 ,  G06F12/00 ,  G11C29/04 ,  G06F12/06

CPC分类号： G06F1/3228 ,  G06F1/3203 ,  G06F3/0659

摘要： Apparatus, systems, and methods are disclosed that operate within a memory to execute internal commands, to suspend the execution of commands during a transfer period, and to execute external commands following the transfer period. Additional apparatus, systems, and methods are disclosed.

摘要翻译： 公开了在存储器内操作以执行内部命令，在传送期间暂停命令的执行以及在传送周期之后执行外部命令的装置，系统和方法。 公开了附加装置，系统和方法。

公开(公告)号：US20080218529A1

公开(公告)日：2008-09-11

申请号：US11574666

申请日：2005-09-05

申请人： Takeshi Okubo ,  Yutaka Ito

发明人： Takeshi Okubo ,  Yutaka Ito

IPC分类号： G09G5/00

CPC分类号： A63F13/52 ,  A63F13/10 ,  A63F13/537 ,  A63F13/57 ,  A63F13/803 ,  A63F2300/303 ,  A63F2300/64 ,  A63F2300/8017 ,  G09B9/05

摘要： An operation input reception unit (201) receives an operation input for a virtual vehicle to be run on the running path. A running condition managing unit (203) manages the running condition of the virtual vehicle based on the received operation input. A load calculation unit (205) calculates a load imposed on a virtual operator in the virtual vehicle, based on the managed running condition. Meanwhile, a symbol drawing unit (401) draws a load symbol whose display position changes according to the calculated load. A tire image drawing unit (402) draws an image of a tire whose display manner changes according to the calculated load. A meter image creating unit (403) creates a meter image including the drawn load symbol and image of the tire. Then, a display control unit (207) displays the created meter image on a predetermined monitor.

摘要翻译： 操作输入接收单元（201）在运行路径上接收要运行的虚拟车辆的操作输入。 运行条件管理单元（203）基于接收的操作输入来管理虚拟车辆的运行状况。 负载计算单元（205）基于管理的运行条件来计算虚拟车辆中的虚拟操作者的负荷。 同时，符号描绘单元（401）根据所计算的负载绘制其显示位置改变的负载符号。 轮胎图像绘制单元（402）根据所计算的载荷绘制显示方式改变的轮胎的图像。 仪表图像创建单元（403）创建包括绘制的负载符号和轮胎的图像的仪表图像。 然后，显示控制单元（207）将所生成的测量图像显示在预定的监视器上。

公开(公告)号：US20080133985A1

公开(公告)日：2008-06-05

申请号：US11968664

申请日：2008-01-03

申请人： Yoshiro RIHO ,  Yutaka Ito

发明人： Yoshiro RIHO ,  Yutaka Ito

IPC分类号： G11C29/08 ,  G06F11/26

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。

公开(公告)号：US07346829B2

公开(公告)日：2008-03-18

申请号：US11092706

申请日：2005-03-30

申请人： Yoshiro Riho ,  Yutaka Ito

发明人： Yoshiro Riho ,  Yutaka Ito

IPC分类号： H03M13/00

CPC分类号： G06F11/1076 ,  G06F11/1012 ,  G11C11/406 ,  G11C29/42 ,  G11C2211/4062

摘要： A test method for a semiconductor device that is provided with an ECC circuit that uses product code that is composed of a first code and a second code for implementing error correction of a memory, the test method includes steps of: obtaining first pass/fail determination results and second pass/fail determination results that are realized by independent correction operations based on the first code and the second code, respectively; recording the results in a first fail memory and a second fail memory, respectively; executing a prescribed logical operation such as an AND operation relating to the contents of the first fail memory and the contents of the second fail memory; and based on the results of the logical operation, remedying both fail bits and potential fail bits.

摘要翻译： 一种半导体器件的测试方法，该半导体器件设置有使用由第一代码组成的产品代码和用于实现存储器的错误校正的第二代码的ECC电路，该测试方法包括以下步骤：获得第一通过/不确定 分别通过基于第一代码和第二代码的独立校正操作实现的结果和第二通过/失败确定结果; 将结果分别记录在第一故障存储器和第二故障存储器中; 执行诸如与第一故障存储器的内容和第二故障存储器的内容有关的AND操作的规定的逻辑操作; 并基于逻辑运算的结果，纠正故障位和潜在故障位。