Abstract:
A processor may include a plurality of processing units for processing instructions, where each processing unit is associated with a discrete instruction queue. Data is read from a data queue selected by each instruction, and a sequencer manages distribution of instructions to the plurality of discrete instruction queues.
Abstract:
A circuit that supports multiple monitors, docking functions, and protected content via one cable. The circuit includes a receiver that receives multiple video streams, each including respective video data, a mux/demux, coupled to the receiver, that determines which video stream to display on a monitor, a low-voltage differential signaling (LVDS) converter, coupled to the mux/demux, that generates an LVDS signal based on the video data of the determined video stream, an LVDS serializer/deserializer, coupled to the LVDS converter, that generates a signal based on the LVDS signal and sends the signal to a display panel of the monitor for display, a transmitter coupled to the mux/demux, and a transmit physical interface (TPI) coupled to the transmitter. The mux/demux sends at least a remainder of the video streams to the transmitter, which sends them to the TPI, which transmits them as output, useable as input to further instances of the circuit.
Abstract:
Various techniques are provided for selectively allocating a buffer adapted to be shared for storage media device data communications and downstream device data communications routed through a hub. For example, in one embodiment, a method includes detecting if one or more downstream devices are connected to one or more downstream device ports of the hub. The method also includes, if any downstream devices are detected: allocating a first portion of the buffer for a storage media device controller, allocating one or more second portions of the buffer for the detected downstream devices, wherein each of the second portions is associated with a corresponding one of the detected downstream devices, and passing the storage media device data communications between a host device and the storage media device controller through the first portion of the buffer and not the second portions of the buffer.
Abstract:
An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.
Abstract:
Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.
Abstract:
A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.
Abstract:
Various techniques are provided for interfacing external devices with host computer systems. In one example, hard drive parameters may be retrieved from a nonvolatile memory of an external hard drive enclosure device in order to register the external device with a host device while the host device provides a low power level to the external device. Following registration of the external device, the host device may provide a high power level to the external device to operate the registered external device. The hard drive parameters may be stored in the nonvolatile memory by a provider of the external device. In another example, the hard drive parameters may be loaded into the nonvolatile memory by appropriate software running on the host device. In yet another example, the external device may read the hard drive parameters from the hard drive while emulating another external device.