Monitor chaining and docking mechanism
    52.
    发明授权
    Monitor chaining and docking mechanism 有权
    监控链接和对接机制

    公开(公告)号:US08395605B2

    公开(公告)日:2013-03-12

    申请号:US13223730

    申请日:2011-09-01

    Abstract: A circuit that supports multiple monitors, docking functions, and protected content via one cable. The circuit includes a receiver that receives multiple video streams, each including respective video data, a mux/demux, coupled to the receiver, that determines which video stream to display on a monitor, a low-voltage differential signaling (LVDS) converter, coupled to the mux/demux, that generates an LVDS signal based on the video data of the determined video stream, an LVDS serializer/deserializer, coupled to the LVDS converter, that generates a signal based on the LVDS signal and sends the signal to a display panel of the monitor for display, a transmitter coupled to the mux/demux, and a transmit physical interface (TPI) coupled to the transmitter. The mux/demux sends at least a remainder of the video streams to the transmitter, which sends them to the TPI, which transmits them as output, useable as input to further instances of the circuit.

    Abstract translation: 通过一条电缆支持多个监视器,对接功能和受保护内容的电路。 电路包括接收多个视频流的接收机,每个视频流包括相应的视频数据,耦合到接收器的多路复用器/多路复用器,其确定在监视器上显示哪个视频流,低压差分信号(LVDS)转换器, 基于所确定的视频流的视频数据产生LVDS信号的多路复用器/解复用器,耦合到LVDS转换器的LVDS串行器/解串器,其基于LVDS信号生成信号并将该信号发送到显示器 用于显示的监视器的面板,耦合到多路复用器/解复用器的发送器以及耦合到发送器的发送物理接口(TPI)。 多路复用器/解复用器将至少一个视频流的剩余部分发送到发送器,发送器将它们发送到TPI,TPI将其作为输出发送,作为电路的其他实例的输入。

    Shared buffer for data communications routed through hub
    53.
    发明授权
    Shared buffer for data communications routed through hub 有权
    用于通过集线器路由的数据通信的共享缓冲区

    公开(公告)号:US08386580B1

    公开(公告)日:2013-02-26

    申请号:US12573019

    申请日:2009-10-02

    CPC classification number: G06F13/4295

    Abstract: Various techniques are provided for selectively allocating a buffer adapted to be shared for storage media device data communications and downstream device data communications routed through a hub. For example, in one embodiment, a method includes detecting if one or more downstream devices are connected to one or more downstream device ports of the hub. The method also includes, if any downstream devices are detected: allocating a first portion of the buffer for a storage media device controller, allocating one or more second portions of the buffer for the detected downstream devices, wherein each of the second portions is associated with a corresponding one of the detected downstream devices, and passing the storage media device data communications between a host device and the storage media device controller through the first portion of the buffer and not the second portions of the buffer.

    Abstract translation: 提供了各种技术,用于选择性地分配适于为存储介质设备数据通信共享的缓冲器和通过集线器路由的下游设备数据通信。 例如,在一个实施例中,一种方法包括检测一个或多个下游设备是否连接到集线器的一个或多个下游设备端口。 该方法还包括:如果检测到任何下游设备:为存储介质设备控制器分配缓冲器的第一部分,为检测到的下游设备分配缓冲器的一个或多个第二部分,其中每个第二部分与 检测到的下游设备中的对应的一个,并且通过缓冲器的第一部分而不是缓冲器的第二部分,将主机设备和存储介质设备控制器之间的存储介质设备数据通信传递给缓冲区。

    Low-Power Class D Amplifier Using Multistate Analog Feedback Loops
    54.
    发明申请
    Low-Power Class D Amplifier Using Multistate Analog Feedback Loops 有权
    低功耗D类放大器,采用多态模拟反馈回路

    公开(公告)号:US20120275493A1

    公开(公告)日:2012-11-01

    申请号:US13097690

    申请日:2011-04-29

    CPC classification number: H03F3/217

    Abstract: An audio amplifier system may include an audio CODEC/output (AOP) path featuring analog class-D amplifiers, and using Natural Sampling Pulse Width Modulation (PWM) to convert an analog input into a series of Rail-to-Rail pulses. The audio signal may be encoded in the average value of the PWM pulse train and may be recovered from the PWM signal by analog low pass filtering. The Class-D amplifiers may be designed with a negative feedback loop/network to compare the output signal with the input signal and suppress non-idealities introduced by the Class-D switching stage. Furthermore, operation of the AOP may be designed according to a separate signal transfer function and a separate noise transfer function, and 2nd order noise shaping may be performed at low power, with an optimized filter included in the feedback loop to achieve the best noise reduction at low power. Operation of the amplifier feedback network may be similar to that of a continuous time, low-pass delta-sigma modulator, but with a PWM loop wrapped around the class-D power amplifier.

    Abstract translation: 音频放大器系统可以包括具有模拟D类放大器的音频CODEC /输出(AOP)路径,并且使用自然采样脉宽调制(PWM)将模拟输入转换成一系列轨至轨脉冲。 音频信号可以以PWM脉冲序列的平均值编码,并且可以通过模拟低通滤波从PWM信号中恢复。 D类放大器可以设计有负反馈回路/网络,以将输出信号与输入信号进行比较,并抑制D类切换级引入的非理想性。 此外,可以根据单独的信号传递函数和单独的噪声传递函数来设计AOP的操作,并且可以以低功率执行二阶噪声整形,其中包括在反馈环路中的优化滤波器以实现最佳降噪 在低功率。 放大器反馈网络的操作可能类似于连续时间低通量Δ-Σ调制器的操作,但是使用包围D类功率放大器的PWM环路。

    Reducing Spurs in Injection-Locked Oscillators
    55.
    发明申请
    Reducing Spurs in Injection-Locked Oscillators 有权
    注射锁定振荡器减少马刺

    公开(公告)号:US20120274370A1

    公开(公告)日:2012-11-01

    申请号:US13097671

    申请日:2011-04-29

    CPC classification number: H03L5/00 H03L7/099 H03L7/24 H04B17/11

    Abstract: Various embodiments of a radio-frequency (RF) transmitter receiver circuit that utilizes an injection locked oscillator may allow for the introduction of a DC offset to correct the RF signal. The DC offset may be adjusted to eliminate (or minimize) even order harmonics to correct for RF effects. The DC offset correction may be performed around the injection locked oscillator to target even order terms.

    Abstract translation: 使用注入锁定振荡器的射频(RF)发射器接收器电路的各种实施例可以允许引入DC偏移来校正RF信号。 可以调整DC偏移以消除(或最小化)偶次谐波以校正RF效应。 可以在注入锁定振荡器周围执行DC偏移校正,以达到偶数阶。

    Wireless communications systems and channel-switching method
    56.
    发明授权
    Wireless communications systems and channel-switching method 有权
    无线通信系统和通道切换方式

    公开(公告)号:US08265041B2

    公开(公告)日:2012-09-11

    申请号:US12106098

    申请日:2008-04-18

    CPC classification number: H04W36/06 H04L1/1607 H04L1/20 H04W36/30

    Abstract: A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.

    Abstract translation: 本文公开了无线通信系统和信道切换方法。 源设备和多个宿设备独立地维护跟踪数据分组错误的相应计数器。 每个设备只有在其计数器达到通道切换阈值后才独立地切换通道。 新的信道切换是由可用信道的索引排序或参考由每个设备维护的全局时钟确定的。 因此,所有设备快速到达公共通道。 系统仅在必要时切换通道,并快速解决相互可接受的通道。 因此,不必要的信道切换被最小化并且数据吞吐量被优化。

    Methods and systems for interfacing bus powered devices with host devices providing limited power levels
    57.
    发明授权
    Methods and systems for interfacing bus powered devices with host devices providing limited power levels 有权
    总线供电设备与提供有限功率水平的主机设备接口的方法和系统

    公开(公告)号:US08185759B1

    公开(公告)日:2012-05-22

    申请号:US12266335

    申请日:2008-11-06

    Abstract: Various techniques are provided for interfacing external devices with host computer systems. In one example, hard drive parameters may be retrieved from a nonvolatile memory of an external hard drive enclosure device in order to register the external device with a host device while the host device provides a low power level to the external device. Following registration of the external device, the host device may provide a high power level to the external device to operate the registered external device. The hard drive parameters may be stored in the nonvolatile memory by a provider of the external device. In another example, the hard drive parameters may be loaded into the nonvolatile memory by appropriate software running on the host device. In yet another example, the external device may read the hard drive parameters from the hard drive while emulating another external device.

    Abstract translation: 提供了用于将外部设备与主机系统进行接口的各种技术。 在一个示例中,可以从外部硬盘驱动器机箱设备的非易失性存储器检索硬盘驱动器参数,以便在主机设备向外部设备提供低功率电平时,向主机设备注册外部设备。 在外部设备注册之后,主机设备可以向外部设备提供高功率电平以操作注册的外部设备。 硬盘驱动器参数可以由外部设备的提供商存储在非易失性存储器中。 在另一示例中,可以通过在主机设备上运行的适当软件将硬盘驱动器参数加载到非易失性存储器中。 在又一示例中,外部设备可以在模拟另一外部设备的同时从硬盘驱动器读取硬盘驱动器参数。

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