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公开(公告)号：US06963249B2
公开(公告)日：2005-11-08
申请号：US10639543
申请日：2003-08-12
CPC分类号： H03L7/24 , H03B5/1215 , H03B5/1228 , H03B5/1243
摘要： The invention relates to the field of electronics and more particularly to the tuning and injection locking of voltage controlled oscillators (VCOs). An improved injection locking circuit is provided which allows the VCO to injection lock with a smaller reference signal and therefore a smaller locking bandwidth (LBW). In order to allow the VCO to injection lock with a lower power reference signal, this invention includes a pre-tuning algorithm to place the VCO frequency such that the desired frequency is in the LBW. Tuning of the VCO is achieved using direct digital tuning that does not require an input reference. Injection locking is performed using a low frequency clock harmonic as the reference signal. More specifically, tuning is accomplished by sub-sampling and digitizing the output signal of the VCO, determining the center frequency, and adjusting the VCO control voltage.
摘要翻译： 本发明涉及电子领域，更具体地涉及压控振荡器（VCO）的调谐和注入锁定。 提供了一种改进的注入锁定电路，其允许VCO以较小的参考信号注入锁定，因此具有较小的锁定带宽（LBW）。 为了允许VCO用较低功率参考信号进行注入锁定，本发明包括预调谐算法以将VCO频率设置为使得期望频率在LBW中。 使用不需要输入参考的直接数字调谐来实现VCO的调谐。 使用低频时钟谐波作为参考信号进行注入锁定。 更具体地，通过对VCO的输出信号进行子采样和数字化，确定中心频率以及调整VCO控制电压来实现调谐。
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公开(公告)号：US06873215B2
公开(公告)日：2005-03-29
申请号：US10629138
申请日：2003-07-28
CPC分类号： G06F1/3246 , G06F1/14 , G06F1/3228
摘要： A power down system and method for an integrated circuit that enables a power down mode to be maintained for a predetermined time is described herein. The power down system comprises an oscillator, a low power oscillator and an oscillator control circuit controlling both the oscillator and the low power oscillator. The oscillator control circuit including at least one real time counter. The oscillator control circuit being so configured that the oscillator is energized when said oscillator control circuit is in a normal mode and that, when a power down signal is received: a) the oscillator control circuit measures an oscillation frequency of the low power oscillator, b) the oscillator control circuit uses the measured oscillation frequency of the low power oscillator to set the real time counter so as to maintain the power down mode for the predetermined time, c) the oscillator control circuit turns off the oscillator and uses the low power oscillator for the duration of the power down.
摘要翻译： 这里描述了一种用于使得能够将停电模式保持预定时间的集成电路的掉电系统和方法。 断电系统包括振荡器，低功率振荡器和控制振荡器和低功率振荡器的振荡器控制电路。 该振荡器控制电路包括至少一个实时计数器。 振荡器控制电路被配置成当所述振荡器控制电路处于正常模式时振荡器被通电，并且当接收到掉电信号时：振荡器控制电路测量低功率振荡器的振荡频率，b ）振荡器控制电路使用测量的低功率振荡器的振荡频率来设置实时计数器，以便在预定时间内保持掉电模式，c）振荡器控制电路关闭振荡器并使用低功率振荡器 在掉电期间。
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公开(公告)号：US20090262709A1
公开(公告)日：2009-10-22
申请号：US12106098
申请日：2008-04-18
CPC分类号： H04W36/06 , H04L1/1607 , H04L1/20 , H04W36/30
摘要： A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.
摘要翻译： 本文公开了无线通信系统和信道切换方法。 源设备和多个宿设备独立地维护跟踪数据分组错误的相应计数器。 每个设备只有在其计数器达到通道切换阈值后才独立地切换通道。 新的信道切换是由可用信道的索引排序或参考由每个设备维护的全局时钟确定的。 因此，所有设备快速到达公共通道。 系统仅在必要时切换通道，并快速解决相互可接受的通道。 因此，不必要的信道切换被最小化并且数据吞吐量被优化。
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公开(公告)号：US07539476B2
公开(公告)日：2009-05-26
申请号：US11374571
申请日：2006-03-13
CPC分类号： H04B1/28
摘要： An improved receiver architecture and method for a wireless transceiver (e.g. for a headphone) is provided whereby the receiver, advantageously, enables the use of only one synthesizer circuit for both the RF-to-IF and IF-to-base band conversion processes which, in turn, provides for lower power consumption. The receiver includes an injection locked local receiver oscillator (Rx LO) which is used for the first mixing stage (i.e. the RF-to-IF conversion). The Rx LO 105 is thereby able to use a high-level harmonic of a relatively low reference frequency signal produced by that synthesizer (e.g. a fractional-N phase locked loop circuit (PLL)). The receiver further includes a tunable Q-enhanced IF filter 110 and complex sub-sampling and mixing down-conversion circuitry for the second conversion stage (i.e. IF-to-baseband conversion). The sampling frequency used for the second conversion stage is a harmonic of the reference frequency derived from the synthesizer (PLL). For example, transceiver channels may be designed on the basis that the RF frequency fRF is assigned a value of (n±¼)·fs, where the frequency fPLL of the PLL may be chosen to be twice the sub-sampling frequency fs and the frequency fRx LO of the Rx LO may be nine times the frequency fPLL.
摘要翻译： 提供了一种用于无线收发器（例如，用于耳机）的改进的接收器架构和方法，由此接收器有利地仅使用一个合成器电路用于RF至IF和IF至基带频带转换过程，其中 反过来又提供较低的功耗。 接收机包括用于第一混频级（即RF至IF转换）的注入锁定本地接收机振荡器（Rx LO）。 因此，Rx LO 105能够使用由该合成器（例如，分数N锁相环电路（PLL））产生的相对低的参考频率信号的高电平谐波。 接收机还包括可调Q增强IF滤波器110和用于第二转换级（即IF到基带转换）的复数次采样和混合下转换电路。 用于第二转换级的采样频率是从合成器（PLL）导出的参考频率的谐波。 例如，可以基于RF频率fRF被分配值（n±¼）.fs来设计收发器信道，其中PLL的频率fPLL可以被选择为子采样频率fs的两倍，并且 Rx LO的频率fRx LO可以是频率fPLL的9倍。
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公开(公告)号：US06836158B2
公开(公告)日：2004-12-28
申请号：US10639544
申请日：2003-08-12
IPC分类号： G11C2702
CPC分类号： G11C27/024 , G11C27/02
摘要： The invention relates to electronic “sample and hold” circuits and, in particular, to such circuits which may implemented in integrated form. A method and circuit are provided for improving isolation during the hold mode of operation of a sampling circuit. An input differential signal is provided to parallel circuit paths (viz. a primary sampling path and an isolation path) which are identical (electronically equivalent) and, therefore, provide the same impedance leading to hold capacitor(s). The circuit paths are configured, relative to the differential inputs, so that any feed through (leakage) of the differential input signal is subtracted (cancelled) during the hold mode.
摘要翻译： 本发明涉及电子“采样和保持”电路，特别涉及可以以集成形式实现的这种电路。 提供了一种用于在采样电路的保持操作模式期间改善隔离的方法和电路。 输入差分信号被提供给相同（电子等效）的并联电路路径（即初级采样路径和隔离路径），并因此提供相同的阻抗，导致保持电容器。 电路路径相对于差分输入配置，以便在保持模式期间减去（消除）差分输入信号的任何馈送（泄漏）。
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公开(公告)号：US08265041B2
公开(公告)日：2012-09-11
申请号：US12106098
申请日：2008-04-18
IPC分类号： H04J3/00
CPC分类号： H04W36/06 , H04L1/1607 , H04L1/20 , H04W36/30
摘要： A wireless communications system and channel-switching method are disclosed herein. A source device and multiple sink devices independently maintain respective counters which track data packet errors. Each device independently switches channels only after its counter reaches a channel-switching threshold. The new channel switched-to is either determined by an indexed ordering of the available channels or by reference to a global clock maintained by each of the devices. Accordingly, all devices quickly arrive at a common channel. The system switches channels only when necessary and resolves quickly to a mutually acceptable channel. Therefore, unnecessary channel switching is minimized and data throughput is optimized.
摘要翻译： 本文公开了无线通信系统和信道切换方法。 源设备和多个宿设备独立地维护跟踪数据分组错误的相应计数器。 每个设备只有在其计数器达到通道切换阈值后才独立地切换通道。 新的信道切换是由可用信道的索引排序或参考由每个设备维护的全局时钟确定的。 因此，所有设备快速到达公共通道。 系统仅在必要时切换通道，并快速解决相互可接受的通道。 因此，不必要的信道切换被最小化并且数据吞吐量被优化。
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