INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION
    61.
    发明申请
    INTERCONNECT STRUCTURE AND METHOD FOR Cu/ULTRA LOW k INTEGRATION 有权
    Cu / ULTRA低k积分的互连结构和方法

    公开(公告)号:US20090194876A1

    公开(公告)日:2009-08-06

    申请号:US12025297

    申请日:2008-02-04

    IPC分类号: H01L23/48 H01L21/4763

    摘要: A semiconductor structure is provided that includes a lower interconnect level including a first dielectric material having at least one conductive feature embedded therein; a dielectric capping layer located on the first dielectric material and some, but not all, portions of the at least one conductive feature; and an upper interconnect level including a second dielectric material having at least one conductively filled via and an overlying conductively filled line disposed therein, wherein the conductively filled via is in contact with an exposed surface of the at least one conductive feature of the first interconnect level by an anchoring area. Moreover, the conductively filled via and conductively filled line of the inventive structure are separated from the second dielectric material by a single continuous diffusion barrier layer. As such, the second dielectric material includes no damaged regions in areas adjacent to the conductively filled line. A method of forming such an interconnect structure is also provided.

    摘要翻译: 提供了一种半导体结构,其包括下互连级,其包括具有嵌入其中的至少一个导电特征的第一介电材料; 位于所述第一电介质材料上的电介质覆盖层以及所述至少一个导电特征的一些但不是全部的部分; 以及包括具有至少一个导电填充通孔的第二介电材料和布置在其中的上覆导电填充线的上部互连水平,其中所述导电填充的通孔与所述第一互连水平的所述至少一个导电特征的暴露表面接触 通过锚定区域。 此外,本发明结构的导电填充通孔和导电填充线通过单个连续扩散阻挡层与第二介电材料分离。 因此,第二电介质材料在与导电填充线相邻的区域中不包括受损区域。 还提供了一种形成这种互连结构的方法。

    Deflection analysis system and method for circuit design
    62.
    发明授权
    Deflection analysis system and method for circuit design 失效
    偏转分析系统及电路设计方法

    公开(公告)号:US07475368B2

    公开(公告)日:2009-01-06

    申请号:US11336524

    申请日:2006-01-20

    IPC分类号: G06F17/50

    CPC分类号: G06F17/50

    摘要: A system, a method and a computer program product for analyzing a circuit design provide for discretizing the circuit design into a series of pixels. A fraction of at least one constituent material is determined for each pixel. A deflection is also determined for each pixel. The deflection is predicated upon a planarizing of the pixel, and it is calculated while utilizing an algorithm that includes the fraction of the at least one constituent material. A series of deflections for the series of pixels may be mapped and evaluated.

    摘要翻译: 用于分析电路设计的系统,方法和计算机程序产品提供将电路设计离散成一系列像素。 确定每个像素的至少一个构成材料的一部分。 还为每个像素确定偏转。 该偏转基于像素的平面化,并且在利用包括至少一个构成材料的分数的算法的同时进行计算。 可以映射和评估一系列像素的一系列偏转。

    STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING
    63.
    发明申请
    STRUCTURE FOR OPTIMIZING FILL IN SEMICONDUCTOR FEATURES DEPOSITED BY ELECTROPLATING 审中-公开
    电镀沉积半导体特性优化结构

    公开(公告)号:US20080284036A1

    公开(公告)日:2008-11-20

    申请号:US12180203

    申请日:2008-07-25

    IPC分类号: H01L23/48 H01L21/44

    摘要: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

    摘要翻译: 提供了一种结构和工艺,其能够减少在金属化期间的不连续性的发生,例如在半导体金属化阵列的边​​缘处的电镀期间形成的空隙或接缝。 该结构包括位于阵列周边周围的金属化棒。 该方法在电镀期间采用该结构。

    Structure for optimizing fill in semiconductor features deposited by electroplating
    64.
    发明授权
    Structure for optimizing fill in semiconductor features deposited by electroplating 失效
    用于优化通过电镀沉积的半导体特征填充的结构

    公开(公告)号:US07446040B2

    公开(公告)日:2008-11-04

    申请号:US11330537

    申请日:2006-01-12

    IPC分类号: H01L21/44

    摘要: A structure and process are provided that are capable of reducing the occurrence of discontinuities within the metallization, such as voiding or seams, formed during electroplating at the edges of semiconductor metallization arrays. The structure includes a metallization bar located around the periphery of the array. The process employs the structure during electroplating.

    摘要翻译: 提供了一种结构和工艺,其能够减少在金属化期间的不连续性的发生,例如在半导体金属化阵列的边​​缘处的电镀期间形成的空隙或接缝。 该结构包括位于阵列周边周围的金属化棒。 该方法在电镀期间采用该结构。

    COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE
    66.
    发明申请
    COMPUTER PROGRAM PRODUCTS FOR DETERMINING STOPPING POWERS OF DESIGN STRUCTURES WITH RESPECT TO A TRAVELING PARTICLE 有权
    计算机程序产品用于确定相对于旅行颗粒的设计结构的停止功能

    公开(公告)号:US20080201681A1

    公开(公告)日:2008-08-21

    申请号:US12111529

    申请日:2008-04-29

    IPC分类号: G06F17/50

    CPC分类号: G06F17/5009 G06F2217/16

    摘要: A computer program product, comprising a computer usable medium having a computer readable program code embodied therein, said computer readable program code including an algorithm adapted to implement a method including the following steps. First, design information of the design structure is provided including a back-end-of-line layer of the integrated circuit which includes N interconnect layers, N being a positive integer. Next, each interconnect layer of the N interconnect layers is divided into multiple pixels. Next, a first path of a traveling particle in a first interconnect layer of the N interconnect layers is determined. Next, M path pixels of the multiple pixels of the first interconnect layer on the first path of the traveling particle are identified, M being a positive integer. Next, a first loss energy lost by the traveling particle due to its completely passing through a first pixel of the M path pixels is determined.

    摘要翻译: 一种计算机程序产品,包括具有包含在其中的计算机可读程序代码的计算机可用介质,所述计算机可读程序代码包括适于实现包括以下步骤的方法的算法。 首先,提供设计结构的设计信息,其包括包括N个互连层的集成电路的后端行层,N是正整数。 接下来,N个互连层的每个互连层被分成多个像素。 接下来,确定N个互连层的第一互连层中的行进粒子的第一路径。 接下来,识别行进粒子的第一路径上的第一互连层的多个像素的M个路径像素,M是正整数。 接下来,确定由于行进粒子完全通过M路径像素的第一像素而损失的第一损失能量。

    Apparatus and method for flattening a warped substrate
    68.
    发明授权
    Apparatus and method for flattening a warped substrate 失效
    使翘曲基材变平的装置和方法

    公开(公告)号:US07214548B2

    公开(公告)日:2007-05-08

    申请号:US10929179

    申请日:2004-08-30

    IPC分类号: H01L21/00

    CPC分类号: H01L21/67288 H01L21/6838

    摘要: A method, apparatus, and computer program product for flattening a warped substrate. The substrate is placed on a planar surface of a clamping apparatus in direct mechanical contact with the planar surface. The substrate comprises surface regions S1, S2, . . . , SN having an average warpage of W1, W2, . . . , WN, respectively, wherein W1≦W2≦ . . . ≦WN and W1≦WN. Zones Z1, Z2, . . . , ZN of the planar surface respectively comprise vacuum port groups G1, G2, . . . , GN. Each group comprises at least one vacuum port. N is at least 2. A vacuum pressure PV1, PV2, . . . , PVN is generated at each vacuum port within group G1, G2, . . . , GN, at a time of T1, T2, . . . , TN to clamp surface region S1, S2, . . . , SN to zone Z1, Z2, . . . , ZN, respectively. The vacuum pressure PV1, PV2, . . . , PVN is maintained at the vacuum ports of group G1, G2, . . . , GN, respectively, until time TN+1. T1

    摘要翻译: 一种用于使翘曲的基底平坦化的方法,装置和计算机程序产品。 基板被放置在与平面表面直接机械接触的夹紧装置的平面表面上。 衬底包括表面区域S 1,S 2,...。 。 。 具有W 1,W 2 2的平均翘曲的S N N N。 。 。 ,其中W 1分别为W 1,其中W 1为= W 2 N。 。 。 < N>和< 1< 1>< N< N> Z区Z 1,Z 2 2,。 。 。 平面的Z N N分别包括真空端口组G 1,G 2,...。 。 。 ,G N N。 每个组包括至少一个真空端口。 N至少为2.真空压力P V1,P2 S2。 。 。 在组G 1,G 2 2中的每个真空端口处产生P 。 。 。 在T 1时,T 2时,G N,N N 3。 。 。 ,T N N夹紧表面区域S 1,S 2,N 2。 。 。 ,Z N 1,Z 2,...,Z N 2。 。 。 ,Z N N 3。 真空压力P ,P , 。 。 ,P N 2保持在组G 1,G 2 2的真空端口。 。 。 ,分别为N N + 1,直到时间T N + 1。 T 1 。 。 。 N + 1 N + 1。

    Building metal pillars in a chip for structure support
    69.
    发明授权
    Building metal pillars in a chip for structure support 有权
    建筑金属支柱在一个芯片的结构支持

    公开(公告)号:US07067902B2

    公开(公告)日:2006-06-27

    申请号:US10726140

    申请日:2003-12-02

    IPC分类号: H01L29/40

    摘要: Stacked via pillars, such as metal via pillars, are provided at different and designated locations in IC chips to support the chip structure during processing and any related processing stresses such as thermal and mechanical stresses. These stacked via pillars connect and extend from a base substrate of the strip to a top oxide cap of the chip. The primary purpose of the stacked via pillars is to hold the chip structure together to accommodate any radial deformations and also to relieve any stress, thermal and/or mechanical, build-up during processing or reliability testing. The stacked via pillars are generally not electrically connected to any active lines or vias, however in some embodiments the stacked via pillars can provide an additional function of providing an electrical connection in the chip.

    摘要翻译: 通过支柱堆叠,例如金属通孔柱,在IC芯片的不同和指定位置处提供,以在加工期间支撑芯片结构以及任何相关的加工应力,例如热和机械应力。 这些堆叠的通孔柱从条带的基底衬底连接并延伸到芯片的顶部氧化物盖。 堆叠的通孔柱的主要目的是将芯片结构保持在一起以适应任何径向变形,并且还可以在处理或可靠性测试期间缓解任何应力,热和/或机械的积累。 堆叠的通孔柱通常不电连接到任何有源线或通孔,但是在一些实施例中,堆叠的通孔柱可以提供在芯片中提供电连接的附加功能。