公开(公告)号：US20080239828A1

公开(公告)日：2008-10-02

申请号：US11765531

申请日：2007-06-20

Applicant: Hee Youl LEE

Inventor： Hee Youl LEE

IPC: G11C16/00

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/344 ,  G11C16/3445

Abstract: An erase operating time can be shortened and an erase operating characteristic can be improved in a flash memory device. The flash memory device includes a plurality of memory cell blocks, an operating voltage generator and a controller. Each of the plurality of memory cell blocks includes memory cells connected to a plurality of word lines. A voltage generator is configured to apply an erase voltage to a memory cell block selected for an erase operation, and change a level of the erase voltage if an attempt of the erase operation is not successful. A controller is configured to control the voltage generator to apply a first erase voltage to a memory cell block selected for an erase operation. The first erase voltage corresponds to a previous erase voltage that was used successfully in completing a previous erase operation. The first erase voltage is an erase voltage that is used in a first erase attempt for the erase operation.

Abstract translation: 可以缩短擦除操作时间并且可以在闪存设备中改善擦除操作特性。 闪存器件包括多个存储单元块，工作电压发生器和控制器。 多个存储单元块中的每一个包括连接到多个字线的存储单元。 电压发生器被配置为向擦除操作选择的存储单元块施加擦除电压，并且如果擦除操作尝试不成功则改变擦除电压的电平。 控制器被配置为控制电压发生器将第一擦除电压施加到为擦除操作选择的存储单元块。 第一擦除电压对应于在完成之前的擦除操作中成功使用的先前擦除电压。 第一擦除电压是在擦除操作的第一擦除尝试中使用的擦除电压。

公开(公告)号：US20080080250A1

公开(公告)日：2008-04-03

申请号：US11856699

申请日：2007-09-17

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34

CPC classification number: G11C16/10

Abstract: The present invention comprises a method of programming a flash memory device comprising performing a first program for programming cells to a first state and a second state higher than the first state, and performing a second program simultaneously together with the first program, for programming cells to the second state and a third state higher than the second state.

Abstract translation: 本发明包括一种编程闪速存储器件的方法，包括执行用于将单元编程为第一状态的第一程序和高于第一状态的第二状态，以及与第一程序一起执行第二程序，用于将单元编程为 第二状态和高于第二状态的第三状态。

公开(公告)号：US07304892B2

公开(公告)日：2007-12-04

申请号：US11594356

申请日：2006-11-06

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/0483 ,  G11C16/30

Abstract: A non-volatile memory device includes first and second memory cell blocks, each including a plurality of memory cells and including a local drain select line, a local source select line, and local word lines. A block selection unit connects given local word lines to global word line, respectively, in response to a block selection signal. A first bias voltage generator is configured to apply at least first and second erase voltages to the global word lines during an erase operation, the first erase voltage being applied to the global word lines during a first erase attempt of the erase operation, the second erase voltage being applied to the global word lines during a second erase attempt, where the second erase attempt is performed if the first erase attempt did not successfully perform the erase operation. The first and second erase voltages being positive voltages. A bulk voltage generator applies a bulk voltage to a bulk of the memory cells during the erase operation.

公开(公告)号：US07259976B2

公开(公告)日：2007-08-21

申请号：US11275281

申请日：2005-12-21

Applicant: Hee Youl Lee ,  Hee Hyun Chang

Inventor： Hee Youl Lee ,  Hee Hyun Chang

IPC: G11C11/34

CPC classification number: G11C16/08 ,  G11C8/08 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/3459 ,  G11C16/3468 ,  G11C16/3481

Abstract: A program control circuit and method thereof selectively controls a supply time of a word line bias voltage depending on the number of program cycles being in progress. Therefore, over-programming of MLCs can be prevented and an overall program time can be shortened.

Abstract translation: 程序控制电路及其方法根据正在进行的程序周期的数量有选择地控制字线偏置电压的供给时间。 因此，可以防止MLC的过度编程，并且可以缩短整个程序时间。

公开(公告)号：US07072226B2

公开(公告)日：2006-07-04

申请号：US11118858

申请日：2005-04-29

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C11/34

CPC classification number: G11C11/14 ,  G11C16/14 ,  G11C16/16

Abstract: Methods are disclosed for erasing a flash memory cell including: (a) a semiconductor substrate, (b) a gate, (c) a source, (d) a drain, (e) a well, the gate including: (1) a tunnel oxide film, (2) a floating gate, (3) a dielectric film and (4) a control gate stacked on the semiconductor substrate. In one of the disclosed methods, a negative bias voltage is applied to the control gate, the source and drain are floated, a positive bias voltage is applied to the well to thereby create a positive bias voltage in the source and the drain, a ground voltage is applied to the well at a first time while maintaining the negative bias voltage a the control gate; and subsequently a ground voltage is applied to the control gate.

公开(公告)号：US06172910B2

公开(公告)日：2001-01-09

申请号：US08984902

申请日：1997-12-04

Applicant: Hee Youl Lee

Inventor： Hee Youl Lee

IPC: G11C1300

CPC classification number: G11C29/50 ,  G11C16/04

Abstract: The present invention disclosed the test cell and method of analyzing using the same which can analysis the cause of degradation of flash EEPROM cell in connection with programming, erasing or reading operation. The test cell comprises a first unit cell consisted of a drain, a source and a floating gate, a control gate; a second unit cell consisted of a drain, a source and a floating gate, control gate formed integrally with the floating gate and control gate of the first unit cell, respectively; and a third unit cell consisted of a drain, a source and a floating gate, a control gate formed integrally with the floating gate and control gate of the first unit cell, respectively.

Abstract translation: 本发明公开了使用该测试单元进行分析的方法，该方法可以分析闪存EEPROM单元与编程，擦除或读取操作相关的劣化原因。 测试单元包括由漏极，源极和浮动栅极组成的第一单元电池，控制栅极; 由漏极，源极和浮置栅极组成的第二单元电池，分别与第一单元电池的浮动栅极和控制栅极整体形成的控制栅极; 以及由漏极，源极和浮置栅极构成的第三单元电池，分别与第一单元的浮置栅极和控制栅极整体形成的控制栅极。