公开(公告)号：US07786505B1

公开(公告)日：2010-08-31

申请号：US11303237

申请日：2005-12-16

Applicant: Kevin J. Yang ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Hyun-Jin Cho

IPC: H01L29/74

CPC classification number: H01L29/7436 ,  H01L27/1027 ,  H01L29/66393

Abstract: Formation of a thyristor-based memory cell is described. A first gate dielectric of the storage element is formed over a base region thereof located in a silicon layer. A transistor is coupled to the storage element via a cathode region located in the silicon layer. The transistor has a gate electrode formed over a second gate dielectric. A spacer is formed at least in part along a sidewall of the gate electrode facing a gate electrode of the storage element. A shallow implant region is formed in the silicon layer responsive at least in part to the spacer. The spacer offsets the shallow implant region from the sidewall. A portion of the shallow implant region is for an extension region. The first gate dielectric and the second gate dielectric are formed at least in part by deposition of a dielectric material.

Abstract translation: 描述了基于晶闸管的存储单元的形成。 存储元件的第一栅极电介质形成在位于硅层中的基极区域上。 晶体管经由位于硅层中的阴极区耦合到存储元件。 晶体管具有形成在第二栅极电介质上的栅电极。 至少部分地沿着栅电极的侧壁与存储元件的栅电极形成间隔物。 在硅层中形成浅的注入区域，至少部分地响应于间隔物。 间隔件从浅侧植入区域偏离侧壁。 浅植入区域的一部分用于延伸区域。 至少部分地通过沉积介电材料形成第一栅极电介质和第二栅极电介质。

公开(公告)号：US20100193351A1

公开(公告)日：2010-08-05

申请号：US12392462

申请日：2009-02-25

Applicant: Soon-Gil YOON ,  Hyun-Jin Cho ,  Kyoung-Woo Park

Inventor： Soon-Gil YOON ,  Hyun-Jin Cho ,  Kyoung-Woo Park

IPC: C23C14/34

CPC classification number: C23C14/16 ,  C23C14/086

Abstract: A method for preparing a transparent conducting film coated with an AZO/Ag/AZO multilayer thin film with low resistivity and high light transmittance, and a transparent conducting film produced by the same method. The method for preparing a transparent conducting film coated with an AZO/Ag/AZO multilayer thin film, includes (a) forming a primary AZO thin film on a substrate using an AZO target doped with Al through a sputtering method; (b) depositing Ag on the primary AZO thin film using the sputtering method to form a deposited Ag layer; and (c) forming a secondary AZO thin film on the Ag thin film using the AZO target doped with Al through a sputtering method.

Abstract translation: 制备涂覆有具有低电阻率和高透光率的AZO / Ag / AZO多层薄膜的透明导电膜的方法和通过相同方法制备的透明导电膜。 制备涂覆有AZO / Ag / AZO多层薄膜的透明导电膜的方法包括：（a）通过溅射法使用掺杂有Al的AZO靶在衬底上形成初级AZO薄膜; （b）使用溅射法在主AZO薄膜上沉积Ag以形成淀积的Ag层; 和（c）使用通过溅射法掺杂Al的AZO靶，在Ag薄膜上形成次级AZO薄膜。

公开(公告)号：US20100016148A1

公开(公告)日：2010-01-21

申请号：US12542266

申请日：2009-08-17

Applicant: Joung Hyeon LIM ,  Young Chul JOUNG ,  Jin Seok OH ,  Hyun Jin CHO ,  Hee Jung CHOI

Inventor： Joung Hyeon LIM ,  Young Chul JOUNG ,  Jin Seok OH ,  Hyun Jin CHO ,  Hee Jung CHOI

IPC: B01J27/24 ,  B01J23/00

CPC classification number: B01J37/0045 ,  B01J23/74 ,  B01J37/082 ,  B82Y30/00 ,  B82Y40/00 ,  C01B32/162

Abstract: An apparatus for preparing a catalyst for carbon nanotubes using spray pyrolysis and a method for preparing the catalyst are disclosed. The apparatus comprises a plurality of raw material tanks, an agitator to mix raw materials respectively supplied from the raw material tanks, a drier to spray the mixture supplied from the agitator and thus to heat and bake the same, and a storage to store a dried material discharged from the drier. The method comprises supplying a plurality of raw materials, mixing the raw materials with one another, spraying the raw material mixture in a liquid state and drying the same at a high temperature, and storing a catalyst generated in the drying process.

Abstract translation: 公开了一种使用喷雾热解制备碳纳米管催化剂的装置及其制备方法。 该装置包括多个原料罐，用于混合从原料罐分别供给的原料的搅拌器，干燥器，喷雾从搅拌器供给的混合物，从而加热并烘烤该混合物;以及储存器， 材料从干燥器中排出。 该方法包括供给多种原料，将原料混合，将原料混合物以液态喷雾并在高温下干燥，并储存在干燥过程中产生的催化剂。

公开(公告)号：US20090162979A1

公开(公告)日：2009-06-25

申请号：US12367891

申请日：2009-02-09

Applicant: Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

Inventor： Kevin J. Yang ,  Farid Nemati ,  Scott Robins ,  James D. Plummer ,  Hyun-Jin Cho

IPC: H01L21/266

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: In a method of fabricating a semiconductor memory device, a thyristor may be formed in a layer of semiconductor material. Carbon may be implanted and annealed in a base-emitter junction region for the thyristor to affect leakage characteristics. The density of the carbon and/or a bombardment energy and/or an anneal therefore may be selected to establish a low-voltage, leakage characteristic for the junction substantially greater than its leakage absent the carbon. In one embodiment, an anneal of the implanted carbon may be performed in common with an activation for other implant regions the semiconductor device.

Abstract translation: 在制造半导体存储器件的方法中，晶闸管可以形成在半导体材料层中。 可以在用于晶闸管的基极 - 发射极结区域中注入和退火碳以影响泄漏特性。 因此可以选择碳的密度和/或轰击能量和/或退火，以建立连接的低电压，泄漏特性，基本上大于其没有碳的泄漏。 在一个实施例中，注入碳的退火可以与半导体器件的其它注入区域的激活共同进行。

公开(公告)号：US20090113538A1

公开(公告)日：2009-04-30

申请号：US12032817

申请日：2008-02-18

Applicant: Young Ik Eom ,  Kwang Sun Ko ,  Hyun Su Jang ,  Hyun Jin Cho ,  Yong Woo Jung ,  Hyun Woo Choi ,  Gye Hyeon Gyeong ,  Jung Hwan Choi ,  Zhen Zhao ,  Tae Hyoung Kim ,  Youn Woo Kim

Inventor： Young Ik Eom ,  Kwang Sun Ko ,  Hyun Su Jang ,  Hyun Jin Cho ,  Yong Woo Jung ,  Hyun Woo Choi ,  Gye Hyeon Gyeong ,  Jung Hwan Choi ,  Zhen Zhao ,  Tae Hyoung Kim ,  Youn Woo Kim

IPC: H04L9/32 ,  G06F21/00 ,  G06F15/16

CPC classification number: H04L63/0807 ,  G06F21/335 ,  G06F21/629 ,  G06F2221/2137 ,  G06F2221/2145 ,  H04L9/3236 ,  H04L9/3247 ,  H04L12/2821 ,  H04L12/2836 ,  H04L63/0876 ,  H04L63/0884 ,  H04L67/125 ,  H04L2209/80

Abstract: Disclosed is a method and system for controlling access for a mobile agent in a home network environment. The method includes the steps of: issuing a role ticket to the mobile agent; verifying access authority to service requested by the mobile agent through the role ticket; and granting the mobile agent access authority to the service. Accordingly, a table for managing access authority of a user is distributed to devices, so that it is possible to provide the mobile agent access control method and system capable of minimizing network traffic in the home network environment.

Abstract translation: 公开了一种用于控制家庭网络环境中的移动代理的访问的方法和系统。 该方法包括以下步骤：向移动代理发放角色凭证; 通过角色授权验证移动代理请求的服务的访问权限; 并授予移动代理对该服务的访问权限。 因此，用于管理用户的访问权限的表被分发给设备，使得可以提供能够最小化家庭网络环境中的网络流量的移动代理访问控制方法和系统。

公开(公告)号：US07460395B1

公开(公告)日：2008-12-02

申请号：US11159447

申请日：2005-06-22

Applicant: Hyun-Jin Cho ,  Farid Nemati

Inventor： Hyun-Jin Cho ,  Farid Nemati

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.

Abstract translation: 新的存储单元只能包含一个晶闸管。 不需要在电池中包括存取晶体管。 在一个实施例中，晶闸管是薄电容耦合晶闸管。 新的存储单元可以以多种方式连接到字，位和控制线，以形成不同的存储器阵列。 公开了字，位和控制线的时序和电压电平。

公开(公告)号：US20080239803A1

公开(公告)日：2008-10-02

申请号：US11692627

申请日：2007-03-28

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

Abstract translation: 提供了一种存储单元，其包括存取晶体管和门控侧栅晶体管（GLT）器件。 存取晶体管包括源节点。 门控侧向晶闸管（GLT）器件包括耦合到存取晶体管的源极节点的阳极节点。

公开(公告)号：US20080012051A1

公开(公告)日：2008-01-17

申请号：US11615982

申请日：2006-12-24

Applicant: Hyun-Jin Cho

Inventor： Hyun-Jin Cho

IPC: H01L29/80

CPC classification number: H01L27/1021 ,  G11C11/404 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/1203

Abstract: A memory cell and methods of making and operating the same are provided. In one aspect, a method of forming a memory cell is provided that includes forming a MOS transistor that has a gate, a source region and a drain region. A bipolar transistor is formed that has a collector, a base and an emitter. The emitter of the bipolar transistor is formed to serve as the source region for the MOS transistor and the base of the bipolar transistor is formed to serve as a capacitive charge storage region for the memory cell.

Abstract translation: 提供了一种存储单元及其制作和操作方法。 一方面，提供一种形成存储单元的方法，包括形成具有栅极，源极区和漏极区的MOS晶体管。 形成具有集电极，基极和发射极的双极晶体管。 双极晶体管的发射极被形成为用于MOS晶体管的源极区域，并且双极晶体管的基极形成为用作存储器单元的电容电荷存储区域。

公开(公告)号：US06653175B1

公开(公告)日：2003-11-25

申请号：US10231805

申请日：2002-08-28

Applicant: Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

Inventor： Farid Nemati ,  Hyun-Jin Cho ,  Scott Robins

IPC: H01L21332

CPC classification number: G11C11/39 ,  H01L29/7436 ,  H01L29/749

Abstract: A semiconductor device having a thyristor-based memory device exhibits improved stability under adverse operating conditions related to temperature, noise, electrical disturbances and light. In one particular example embodiment of the present invention, a semiconductor device includes a thyristor-based memory device that uses a shunt that effects a leakage current in the thyristor. The thyristor includes a capacitively-coupled control port and anode and cathode end portions. Each of the end portions has an emitter region and an adjacent base region. In one implementation, the current shunt is located between the emitter and base region of one of the end portions of the thyristor and is configured and arranged to shunt low-level current therebetween. In connection with an example embodiment, it has been discovered that shunting current in this manner improves the ability of the device to operate under adverse conditions that would, absent the shunt, result in inadvertent turn on, while keeping the standby current of the memory device to an acceptably low level.

Abstract translation: 具有基于晶闸管的存储器件的半导体器件在与温度，噪声，电扰动和光线相关的不利操作条件下表现出改进的稳定性。 在本发明的一个具体示例实施例中，半导体器件包括基于晶闸管的存储器件，其使用在晶闸管中产生漏电流的分流器。 晶闸管包括电容耦合控制端口和阳极和阴极端部分。 每个端部具有发射极区域和相邻的基极区域。 在一个实施方案中，电流分流器位于晶闸管的一个端部的发射极和基极区域之间，并且被配置和布置成在它们之间分流低电平电流。 结合示例性实施例，已经发现，以这种方式分流电流提高了器件在不利条件下操作的能力，这种不利条件将在不存在分流的情况下导致无意中导通，同时保持存储器件的待机电流 达到可接受的低水平。

公开(公告)号：US06653174B1

公开(公告)日：2003-11-25

申请号：US10023052

申请日：2001-12-17

Applicant: Hyun-Jin Cho ,  Andrew Horch ,  Scott Robins ,  Farid Nemati

Inventor： Hyun-Jin Cho ,  Andrew Horch ,  Scott Robins ,  Farid Nemati

IPC: H01L21332

CPC classification number: H01L29/74 ,  G11C11/39 ,  H01L27/0617 ,  H01L27/0688 ,  H01L27/1023 ,  H01L27/1027 ,  H01L27/11 ,  H01L27/1104 ,  H01L29/41716 ,  H01L29/42308 ,  H01L29/749 ,  H01L29/87

Abstract: A semiconductor device having a thyristor is manufactured in a manner that reduces or eliminates manufacturing difficulties commonly experienced in the formation of such devices. According to an example embodiment of the present invention, a thyristor is formed having some or all of the body of the thyristor extending above a substrate surface of a semiconductor device. The semiconductor device includes at least one transistor having source/drain regions formed in the substrate prior to the formation of the thyristor. One or more layers of material are deposited on the substrate surface and used to form a portion of a body of the thyristor that includes anode and cathode end portions. Each end portion is formed having a base region and an emitter region, and at least one of the end portions includes a portion that is in the substrate and electrically coupled to the transistor. A control port is formed capacitively coupled to at least one of the base regions.

Abstract translation: 制造具有晶闸管的半导体器件以减少或消除在形成这些器件时通常经历的制造困难的方式。 根据本发明的示例性实施例，形成了晶闸管，其中半导体器件的衬底表面上方延伸有晶闸管的一部分或全部。 半导体器件包括至少一个晶体管，其在形成晶闸管之前在衬底中形成有源/漏区。 一层或多层材料沉积在衬底表面上，并用于形成包括阳极和阴极端部的晶闸管体的一部分。 每个端部形成为具有基极区域和发射极区域，并且至少一个端部部分包括位于衬底中并电耦合到晶体管的部分。 形成电容耦合到至少一个基极区域的控制端口。