公开(公告)号：US20100169544A1

公开(公告)日：2010-07-01

申请号：US12356306

申请日：2009-01-20

Applicant: Young-Ik EOM ,  Dong-Kun SHIN ,  Hyun-Jin CHO

Inventor： Young-Ik EOM ,  Dong-Kun SHIN ,  Hyun-Jin CHO

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F2212/7201 ,  G06F2212/7202 ,  G06F2212/7203

Abstract: A method for distributing log block associativity in log buffer-based flash translation layer (FTL) includes, if write request on page p is generated, checking whether log block associated with corresponding data block that write request is generated exists or not by checking log block mapping table storing mapping information between data blocks and log blocks, wherein the associativity of each log block to data block is set to equal to or less than predetermined value K in advance, and K is a natural number, if log block associated with corresponding data block that write request is generated exists, checking whether associated log block is random log block or sequential log block, and if associated log block is random log block, writing data that write request is generated in first free page of random log block.

Abstract translation: 在基于日志缓冲的闪存转换层（FTL）中分配日志块关联性的方法包括：如果生成了第p页上的写请求，则通过检查日志块来检查是否存在与写入请求相关联的数据块相关联的日志块是否存在 映射表存储数据块和日志块之间的映射信息，其中每个日志块与数据块的相关性被预先设置为等于或小于预定值K，并且如果与对应数据相关联的日志块，则K是自然数 产生写请求的块，检查关联的日志块是随机日志块还是顺序日志块，如果关联的日志块是随机日志块，则写入请求的数据在随机日志块的第一个空闲页中生成。

公开(公告)号：US20080239803A1

公开(公告)日：2008-10-02

申请号：US11692627

申请日：2007-03-28

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: G11C11/39

CPC classification number: G11C11/39

Abstract: A memory cell is provided which includes an access transistor and a gated lateral thyristor (GLT) device. The access transistor includes a source node. The gated lateral thyristor (GLT) device includes an anode node coupled to the source node of the access transistor.

Abstract translation: 提供了一种存储单元，其包括存取晶体管和门控侧栅晶体管（GLT）器件。 存取晶体管包括源节点。 门控侧向晶闸管（GLT）器件包括耦合到存取晶体管的源极节点的阳极节点。

公开(公告)号：US20090108353A1

公开(公告)日：2009-04-30

申请号：US11932136

申请日：2007-10-31

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L29/7853 ,  H01L29/66795

Abstract: A FinFET structure is fabricated by patterning a semiconductor substrate to form a nonplanar semiconductor structure including a first fin, a second fin substantially parallel to the first fin, and an inter-fin semiconductor strip coupled therebetween. The first fin, the second fin, and the inter-fin semiconductor strip each extend from a drain region to a source region. A gate dielectric layer is formed on the first and second fins and the inter-fin semiconductor strip in a gate region substantially orthogonal to the first and second fins and between the drain and source region. A gate electrode layer is formed on the gate dielectric layer. The semiconductor substrate may be a silicon-on-insulator (SOI) material comprising a buried oxide layer (BOX) having a silicon layer formed thereon.

Abstract translation: 通过图案化半导体衬底以形成非平面半导体结构来制造FinFET结构，该非平面半导体结构包括第一鳍片，基本上平行于第一鳍片的第二鳍片和耦合在其间的鳍间半导体条带。 第一鳍片，第二鳍片和鳍片间半导体条每个从漏极区域延伸到源极区域。 在与第一和第二鳍片基本正交并且在漏极和源极区域之间的栅极区域中的第一和第二鳍片和鳍间半导体条上形成栅极电介质层。 栅极电极层形成在栅极电介质层上。 半导体衬底可以是包括其上形成有硅层的掩埋氧化物层（BOX）的绝缘体上硅（SOI）材料。

公开(公告)号：US20110204429A1

公开(公告)日：2011-08-25

申请号：US13098193

申请日：2011-04-29

Applicant: Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

Inventor： Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

IPC: H01L27/108

CPC classification number: H01L27/10802 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/1087 ,  H01L29/7841

Abstract: A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.

Abstract translation: 提供一种包括沟槽电容器和存取晶体管的半导体存储单元。 存取晶体管包括源区域，漏极区域，覆盖沟槽电容器的栅极结构以及将漏极区域耦合到源极区域的有源体区域。 有源体区域直接接触沟槽电容器。

公开(公告)号：US20100144106A1

公开(公告)日：2010-06-10

申请号：US12330282

申请日：2008-12-08

Applicant: Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

Inventor： Hyun-Jin CHO ,  Sang H. DHONG ,  Jung-Suk GOO ,  Gurupada MANDAL

IPC: H01L21/8242

CPC classification number: H01L27/10802 ,  H01L27/108 ,  H01L27/1082 ,  H01L27/1087 ,  H01L29/7841

Abstract: A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.

Abstract translation: 提供一种制造存储单元的方法。 在包括半导体层的半导体结构中形成沟槽，并且在沟槽中形成沟槽电容器。 将导电性确定杂质注入到半导体结构中以在直接耦合到沟槽电容器的半导体层中形成阱区。 形成覆盖阱区域的一部分的栅极结构。 然后将确定电导的离子注入阱区的其它部分以形成源区和漏区，并且在源区和漏区之间限定有源体区。 有源体区域直接接触沟槽电容器。

公开(公告)号：US20090298238A1

公开(公告)日：2009-12-03

申请号：US12128908

申请日：2008-05-29

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: H01L21/332

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817

Abstract: A method for fabricating a memory device is provided. A semiconductor layer is provided that includes first, second, third and fourth well regions of a first conductivity type in the semiconductor layer. A first gate structure overlies the first well region, a second gate structure overlies the second well region, a third gate structure overlies the third well region and is integral with the second gate structure, and a fourth gate structure overlies the fourth well region. Sidewall spacers are formed adjacent a first sidewall of the first gate structure and sidewalls of the second through fourth gate structures. In addition, an insulating spacer block is formed overlying a portion of the first well region and a portion of the first gate structure. The insulating spacer block is adjacent a second sidewall of the first gate structure. A first source region is formed adjacent the first gate structure, a common drain/cathode region is formed between the first and second gate structures, a second source region is formed adjacent the third gate structure, a common drain/source region is formed between the third and fourth gate structures, and a drain region is formed adjacent the fourth gate structure. A first base region is formed that extends into the first well region under the insulating spacer block adjacent the first gate structure, and an anode region is formed in the first well region that extends into the first well region adjacent the first base region.

Abstract translation: 提供了一种用于制造存储器件的方法。 提供半导体层，其包括在半导体层中的第一导电类型的第一，第二，第三和第四阱区。 第一栅极结构覆盖第一阱区，第二栅极结构覆盖第二阱区，第三栅极结构覆盖第三阱区，并与第二栅极结构成一体，第四栅极结构覆盖第四阱区。 在第一栅极结构的第一侧壁和第二至第四栅极结构的侧壁附近形成侧壁间隔物。 此外，绝缘间隔块形成在第一阱区的一部分和第一栅结构的一部分之上。 绝缘间隔块与第一栅极结构的第二侧壁相邻。 第一源极区域与第一栅极结构相邻地形成，在第一和第二栅极结构之间形成共同的漏极/阴极区域，在第三栅极结构附近形成第二源极区域，在第二栅极/ 第三和第四栅极结构，并且与第四栅极结构相邻形成漏极区。 形成第一基极区域，其延伸到与第一栅极结构相邻的绝缘间隔块下方的第一阱区域中，并且阳极区域形成在第一阱区域中，该第一阱区域延伸到与第一基极区域相邻的第一阱区域。

公开(公告)号：US20090296463A1

公开(公告)日：2009-12-03

申请号：US12128901

申请日：2008-05-29

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: G11C11/39

CPC classification number: H01L27/1027 ,  G11C11/39 ,  H01L27/0817

Abstract: A memory device is provided which includes a write bit line, a read bit line, and at least one memory cell. The memory cell includes a write access transistor, a read access transistor coupled to the read bit line and to the first write access transistor, and a gated-lateral thyristor (GLT) device coupled to the first write access transistor. Among its many features, the memory cell prevents read disturbances during read operations by decoupling the read and write bit lines.

Abstract translation: 提供了一种存储器件，其包括写位线，读位线和至少一个存储器单元。 存储单元包括写入存取晶体管，耦合到读取位线和第一写入存取晶体管的读取存取晶体管，以及耦合到第一写入存取晶体管的门控晶闸管（GLT）器件。 在其许多特征中，存储器单元通过去读取和写入位线来防止在读取操作期间的读取干扰。

公开(公告)号：US20080242009A1

公开(公告)日：2008-10-02

申请号：US11692313

申请日：2007-03-28

Applicant: Hyun-Jin CHO

Inventor： Hyun-Jin CHO

IPC: H01L21/332

CPC classification number: H01L27/1027

Abstract: A method is provided for fabricating a memory device. A semiconductor substrate is provided which includes a first well region having a first conductivity type, a second well region having the first conductivity type, a first gate structure overlying the first well region and the second gate structure overlying the second well region. An insulating material layer is conformally deposited overlying exposed portions of the semiconductor substrate. Photosensitive material is provided over a portion of the insulating material layer which overlies a portion of the second well region. The photosensitive material exposes portions of the insulating material layer. The exposed portions of the insulating material layer are anisotropically etched to provide a sidewall spacer adjacent a first sidewall of the second gate structure, and an insulating spacer block formed overlying a portion of the second gate structure and adjacent a second sidewall of the second gate structure. A drain region and a source/base region are formed in the semiconductor substrate adjacent the first gate structure and a cathode region is formed in the semiconductor substrate adjacent the second gate structure. The drain region, the source/base region, and the cathode region have a second conductivity type. An anode region of the first conductivity type is formed adjacent the second gate structure in a portion of the source/base region.

Abstract translation: 提供了一种用于制造存储器件的方法。 提供一种半导体衬底，其包括具有第一导电类型的第一阱区，具有第一导电类型的第二阱区，覆盖第一阱区的第一栅极结构和覆盖第二阱区的第二栅极结构。 绝缘材料层被共面沉积在半导体衬底的暴露部分上。 在绝缘材料层的覆盖在第二阱区的一部分上的部分上提供感光材料。 感光材料暴露绝缘材料层的部分。 绝缘材料层的暴露部分被各向异性蚀刻以提供与第二栅极结构的第一侧壁相邻的侧壁间隔件，以及形成在第二栅极结构的一部分上并且邻近第二栅极结构的第二侧壁的绝缘间隔块 。 漏极区域和源极/基极区域形成在与第一栅极结构相邻的半导体衬底中，并且阴极区域形成在邻近第二栅极结构的半导体衬底中。 漏极区域，源极/基极区域和阴极区域具有第二导电类型。 第一导电类型的阳极区域在源极/基极区域的一部分中与第二栅极结构相邻形成。

公开(公告)号：US20110128721A1

公开(公告)日：2011-06-02

申请号：US12819592

申请日：2010-06-21

Applicant: Byoung-Ho CHEONG ,  Guk-Hyun KIM ,  Oleg PRUDNIKOV ,  Seung-Won PARK ,  Hyun-Jin CHO

Inventor： Byoung-Ho CHEONG ,  Guk-Hyun KIM ,  Oleg PRUDNIKOV ,  Seung-Won PARK ,  Hyun-Jin CHO

IPC: G02F1/13357 ,  H01J9/24

CPC classification number: G02F1/133603 ,  G02F1/133611

Abstract: A backlight unit includes a light source substrate on which a light source is mounted, a first light source plate which is disposed on the light source substrate and includes a cylindrical aperture corresponding to the light source, and a second light source plate which is disposed on the first light source plate and includes a partial transmission pattern on a bottom surface thereof. The partial transmission pattern corresponds to the aperture and allows part of light emitted from the light source to pass therethrough.

Abstract translation: 背光单元包括其上安装有光源的光源基板，设置在光源基板上并包括与光源对应的圆筒孔的第一光源板和设置在光源基板上的第二光源板 第一光源板并且在其底表面上包括部分透射图案。 部分透射图案对应于孔径，并且允许从光源发射的光的一部分通过。