公开(公告)号：US20140070734A1

公开(公告)日：2014-03-13

申请号：US13699810

申请日：2012-09-09

Applicant: James Aweya ,  Nayef AlSindi

Inventor： James Aweya ,  Nayef AlSindi

IPC: H02P29/00 ,  H02P5/46

CPC classification number: H02P5/46 ,  H02P5/74 ,  H02P23/22

Abstract: This invention relates to methods and devices for motor speed control. The invention has particular application in the control of motors over packet networks. In embodiments of the invention, phase-locked loop principles are used to remotely control the speed of an electric motor over a packet network. The setpoint for the motor is supplied by arriving timestamps from a speed-mapped variable frequency source. The shaft speed of the motor is measured with a tachometer with its output proportional to the motor speed. Any deviation of the actual speed from the setpoint is amplified by the power amplifier whose output drives the motor. Speed control over packet networks allow smoother operation of a process, acceleration control, different operating speeds for each process recipe, compensation for changing process variables, slow operation for setup purposes, adjustments to the rate of production, accurate positioning, and control torque or tension of a system.

Abstract translation: 本发明涉及电机速度控制的方法和装置。 本发明特别适用于通过分组网络控制电动机。 在本发明的实施例中，使用锁相环原理来远程控制分组网络上的电动机的速度。 电机的设定值由速度映射的可变频率源的到达时间戳提供。 电机轴转速用转速计测量，其转速与电机转速成比例。 实际速度与设定值的任何偏差由输出驱动电机的功率放大器放大。 通过分组网络的速度控制可以使流程更加顺畅，加速控制，每个过程配方的不同运行速度，改变过程变量的补偿，设定目的的缓慢操作，生产率的调整，精确的定位和控制扭矩或张力 的系统。

公开(公告)号：US20130282875A1

公开(公告)日：2013-10-24

申请号：US13924714

申请日：2013-06-24

Applicant: James AWEYA ,  Luis Orozco BARBOSA

Inventor： James AWEYA ,  Luis Orozco BARBOSA

IPC: H04L29/08

CPC classification number: H04L67/02 ,  H03L7/08 ,  H03L7/093 ,  H03L7/18 ,  H04J3/0667

Abstract: A timing system for time synchronization between a time server and a time client. The timing system includes a time server for generating current timestamp information and a time client having a phase-locked loop driven client clock counter. The time client periodically exchanges time transfer protocol messages with the time server over a packet network, and calculates an estimated client time based on the timestamp information. The phase-locked loop in the time client receives periodic signals representing the estimated server time as its input and calculates a signal which represents the error difference between the estimated server time and the time indicated by the time client clock counter. The error difference eventually converges to zero or a given error range indicating the time presented by the client clock counter, which is driven by the phase-locked loop having locked onto the time of the time server.

Abstract translation: 时间服务器与时间客户端之间的时间同步的定时系统。 定时系统包括用于产生当前时间戳信息的时间服务器和具有锁相环驱动的客户时钟计数器的时间客户端。 时间客户端通过分组网络周期性地与时间服务器交换时间传送协议消息，并且基于时间戳信息来计算估计的客户端时间。 时间客户端中的锁相环接收表示估计服务器时间的周期信号作为其输入，并计算表示估计服务器时间与时间客户时钟计数器指示的时间之间的误差的信号。 误差差最终收敛到零或给定的误差范围，指示由锁定在时间服务器的时间上的锁相环驱动的客户时钟计数器所呈现的时间。

公开(公告)号：US20130034197A1

公开(公告)日：2013-02-07

申请号：US13204079

申请日：2011-08-05

Applicant: James Aweya ,  Saleh Al Araji

Inventor： James Aweya ,  Saleh Al Araji

IPC: H04L7/04

CPC classification number: H04J3/0664 ,  H03L7/0807 ,  H03L7/099 ,  H03L7/0991 ,  H03L7/0994 ,  H03L2207/50 ,  H04J3/0667

Abstract: The present invention provides a method of synchronising the frequency of a slave clock to that of a master, preferably using a packet network. An aspects of the invention provide a method of synchronizing the frequency of a slave clock in a slave device to a master clock in a master device, the method including the steps of: a) receiving in the slave device a first message from said master device having a first time-stamp which is a time-stamp of said master clock indicating the time of sending of said first message; b) extracting said time-stamp from said message and initializing a counter in the slave device which counts an output of said slave clock; c) receiving in the slave device a further message from said master device and reading the value of said counter at the time of receipt of said further message; d) extracting a further time-stamp which is the precise time of sending of the further message according to said master clock; e) determining an error signal which is representative of the difference between said value of the counter and the difference between said first and further time-stamps; and f) adjusting the frequency of said slave clock based on said error signal. An apparatus for synchronizing the frequency of a clock in a slave device which is communicatively coupled to a master device is also provided.

Abstract translation: 本发明提供了一种使从属时钟的频率与主机的频率同步的方法，优选地使用分组网络。 本发明的一个方面提供了一种使从设备中的从时钟频率与主设备中的主时钟同步的方法，所述方法包括以下步骤：a）在从设备中接收来自所述主设备的第一消息 具有第一时间戳，其是表示发送所述第一消息的时间的所述主时钟的时间戳; b）从所述消息中提取所述时间戳并初始化从属设备中计数所述从时钟的输出的计数器; c）在所述从设备中从所述主设备接收另外的消息并在接收到所述另外的消息时读取所述计数器的值; d）提取作为根据所述主时钟发送另外的消息的精确时间的另外的时间戳; e）确定代表所述计数器的所述值与所述第一和其它时间戳之间的差的差的误差信号; 以及f）基于所述误差信号调整所述从时钟的频率。 还提供了一种用于使通信地耦合到主设备的从设备中的时钟频率同步的设备。

公开(公告)号：US20110243156A1

公开(公告)日：2011-10-06

申请号：US13162242

申请日：2011-06-16

Applicant: James Aweya ,  Michel Ouellette

Inventor： James Aweya ,  Michel Ouellette

IPC: H04J3/00 ,  H04J3/06

CPC classification number: H04J3/065 ,  H04J3/0682 ,  H04J3/0697 ,  H04L67/06 ,  H04W56/0055

Abstract: Techniques for time transfer via signal encoding are disclosed. In one particular exemplary embodiment, the techniques may be realized as a method for time transfer via signal encoding comprising generating a time service ordered-set for inclusion in a physical coding sublayer frame of a physical layer device, generating time service data for inclusion in the physical coding sublayer frame of the physical layer device, and transmitting the physical coding sublayer frame.

Abstract translation: 公开了通过信号编码进行时间传递的技术。 在一个特定的示例性实施例中，这些技术可以被实现为用于经由信号编码的时间传送的方法，包括生成用于包括在物理层设备的物理编码子层帧中的时间服务有序集，生成包括在 物理层设备的物理编码子层帧，并发送物理编码子层帧。

公开(公告)号：US20100118894A1

公开(公告)日：2010-05-13

申请号：US12268008

申请日：2008-11-10

Applicant: James AWEYA ,  Michel OUELLETTE ,  Delfin Y. MONTUNO

Inventor： James AWEYA ,  Michel OUELLETTE ,  Delfin Y. MONTUNO

IPC: H04J3/06

CPC classification number: H04L7/0079 ,  G06F1/0328 ,  H03L7/0805 ,  H03L7/085 ,  H03L7/089 ,  H03L2207/50 ,  H04J3/0632 ,  H04J3/0658

Abstract: A method, system and master service interface transfer differential timing over a packet network. The transmitting service interface receives a service clock and is coupled to a receiving service interface through a network backplane. A primary reference clock is provided to time the network backplane. The primary reference clock and the service clock are used to synthesize a copy of the service clock connected to the transmitting service interface. A first control word containing an error differential between the service clock and the synthesized copy of the service clock is generated and transmitted through the network backplane via a packet. The first control word, together with the primary reference clock, is used to recreate the service clock for timing the receiving service interface.

Abstract translation: 一种方法，系统和主服务接口通过分组网络传输差分定时。 发送业务接口接收业务时钟，通过网络背板耦合到接收业务接口。 提供主参考时钟来对网络背板进行时间。 主参考时钟和服务时钟用于合成连接到发送服务接口的业务时钟的副本。 生成服务时钟和服务时钟的合成副本之间的误差的第一个控制字，并经由分组通过网络背板发送。 第一个控制字与主参考时钟一起用于重新创建用于定时接收服务接口的服务时钟。

公开(公告)号：US20090276542A1

公开(公告)日：2009-11-05

申请号：US12114252

申请日：2008-05-02

Applicant: James AWEYA ,  Luis Orozco BARBOSA

Inventor： James AWEYA ,  Luis Orozco BARBOSA

IPC: G06F15/16

CPC classification number: H04L67/02 ,  H03L7/08 ,  H03L7/093 ,  H03L7/18 ,  H04J3/0667

Abstract: A timing system for time synchronization between a time server and a time client over a packet network. The timing system includes a time server for generating current timestamp information and a time client having a phase-locked loop driven client clock counter. The time client periodically exchanges time transfer protocol messages with the time server over the packet network, and calculates an estimated client time based on the timestamp information. The phase-locked loop in the time client receives periodic signals representing the estimated server time as its input and calculates a signal which represents the error difference between the estimated server time and the time indicated by the time client clock counter. The error difference eventually converges to zero or a given error range indicating the time presented by the client clock counter, which is driven by the phase-locked loop having locked onto the time of the time server.

Abstract translation: 时间服务器和分组网络上的时间客户端之间的时间同步的定时系统。 定时系统包括用于产生当前时间戳信息的时间服务器和具有锁相环驱动的客户时钟计数器的时间客户端。 时间客户端通过分组网络周期性地与时间服务器交换时间传送协议消息，并且基于时间戳信息来计算估计的客户端时间。 时间客户端中的锁相环接收表示估计服务器时间的周期信号作为其输入，并计算表示估计服务器时间与时间客户时钟计数器指示的时间之间的误差的信号。 误差差最终收敛到零或给定的误差范围，指示由锁定在时间服务器的时间上的锁相环驱动的客户时钟计数器所呈现的时间。

公开(公告)号：US07613268B2

公开(公告)日：2009-11-03

申请号：US11394705

申请日：2006-03-31

Applicant: James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

Inventor： James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

IPC: H03D3/24

CPC classification number: H03L7/08 ,  H03L2207/50

Abstract: A method and apparatus for designing a PLL enables initial component characteristics and design specifications of the PLL to be specified. Time constants for a loop filter that would be required to create a PLL having the desired design specifications and component characteristics are then computed. The performance or behavior characteristics of the PLL may then be computed for the PLL given the time constants and the initial set of components, to determine whether the performance of the PLL would be considered satisfactory. For example, PLL design software may determine whether a PLL would be sufficiently stable if it was to be created using the particular selected components given the required design specifications. Where the PLL does not meet particular behavior characteristics, the PLL design software may provide guidance as to what component characteristics would improve performance of the PLL. Designed PLLs may be used for timestamp based clock synchronization.

Abstract translation: 用于设计PLL的方法和装置使得能够指定PLL的初始组件特性和设计规范。 然后计算创建具有所需设计规范和组件特性的PLL所需的环路滤波器的时间常数。 然后可以为给定时间常数和初始组件组的PLL计算PLL的性能或行为特性，以确定PLL的性能是否被认为是令人满意的。 例如，PLL设计软件可以确定PLL是否将足够稳定，如果要在给定所需设计规范的情况下使用特定的选定组件创建PLL。 在PLL不符合特定行为特性的情况下，PLL设计软件可以提供关于什么组件特性将提高PLL性能的指导。 设计的PLL可用于基于时间戳的时钟同步。

公开(公告)号：US07590210B2

公开(公告)日：2009-09-15

申请号：US11172100

申请日：2005-06-30

Applicant: James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

Inventor： James Aweya ,  Delfin Y. Montuno ,  Michel Ouellette ,  Kent Felske

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H03L7/0992 ,  H04J3/0664

Abstract: A first level of control over operation of slave Digitally Controlled Frequency Selectors (DCFSs), such as DCOs or DDSs, may occur by periodic transmission of control words from the master clock to the slave clocks. To allow enhanced control over the output of the slave clocks, the frequency of the local oscillator used to generate the synthesized output of the master clock may also be conveyed to the slave clocks to allow a second level of control to take place. The second level of control allows the local oscillators at the slave clocks to lock onto the frequency of the master local oscillator to thereby allow the slave local oscillators to operate the slave DCFSs using the same local oscillator frequency. The first level of control synchronizes operation of the DCFSs while the second level control prevents instabilities in the local oscillators from causing long term drift between the slave and master clock outputs. Timestamps may be used to synchronize the master and slave local oscillators.

Abstract translation: 通过从主时钟到从时钟的控制字的周期性传输，可能会发生对从属数字控制频率选择器（DCFS）（如DCO或DDS）的操作的第一级控制。 为了增强对从时钟的输出的控制，用于产生主时钟的合成输出的本地振荡器的频率也可以被传送到从时钟，以允许进行第二级控制。 第二级控制允许从时钟的本地振荡器锁定到主本地振荡器的频率，从而允许从局部振荡器使用相同的本地振荡器频率来操作从DCFS。 第一级控制同步DCFS的操作，而第二级控制防止本地振荡器中的不稳定性引起从机和主时钟输出之间的长期漂移。 时间戳可用于同步主从本地振荡器。

公开(公告)号：US20080231511A1

公开(公告)日：2008-09-25

申请号：US11689660

申请日：2007-03-22

Applicant: Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette ,  Kent Felske

Inventor： Delfin Y. Montuno ,  James Aweya ,  Michel Ouellette ,  Kent Felske

IPC: G01S1/24 ,  G01S3/02

CPC classification number: G01S5/06

Abstract: A novel beacon-based position location technique for efficient location discovery of untethered clients in packet networks is disclosed. The position location technique utilizes the time-difference-of-arrival (“TDOA”) of a first signal transmitted by a beacon of known location and a second signal transmitted by an untethered client. The TDOA of these two signals is measured locally by at least three non-collinear signal receivers. For each of the receivers, the TDOA is used to calculate a perceived distance to the client. A circle is then calculated for each receiver, centered on the receiver and having a radius equal to the perceived distance. At least two lines defined by points of intersection of the calculated circles are then calculated. The point of intersection of the lines represents the location of the client. To facilitate operation, the signal receivers may be arranged on vertices which define a convex polygon as viewed from above. The location system requires no time (time-of-day) synchronization of the signal receivers, and only the coarse frequency synchronization, on the order of, tens of parts-per-million (ppm). The technique even works for the case where the signal receivers are run asynchronously, provided the frequency accuracies of the signal receivers are on the order of about 50ppm or better. The technique introduces no communication overhead for the beacon, client and signal receivers. Further, the computation overhead at the signal receivers is relatively low because the location detection algorithm involves only simple algebraic operations over scalar values.

Abstract translation: 公开了一种新颖的基于信标的位置定位技术，用于在分组网络中无阻塞客户端的有效位置发现。 位置定位技术利用由已知位置的信标发送的第一信号的到达时间差（“TDOA”）和由无阻塞客户端发送的第二信号。 这两个信号的TDOA由至少三个非共线信号接收器本地测量。 对于每个接收机，TDOA用于计算到客户端的感知距离。 然后，以接收机为中心并且具有等于感知距离的半径的每个接收机计算一个圆。 然后计算由计算圆的交点定义的至少两条线。 线的交点表示客户端的位置。 为了便于操作，信号接收器可以被布置在从上方观察的限定凸多边形的顶点上。 定位系统不需要信号接收机的时间（时间）同步，只需要几十分之一百万分之几的粗略频率同步（ppm）。 该技术甚至适用于信号接收机异步运行的情况，只要信号接收机的频率精度约为50ppm或更高。 该技术不引入信标，客户端和信号接收机的通信开销。 此外，信号接收机的计算开销相对较低，因为位置检测算法仅涉及标量值的简单代数运算。

公开(公告)号：US20080144515A1

公开(公告)日：2008-06-19

申请号：US11609966

申请日：2006-12-13

Applicant: Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske

Inventor： Michel Ouellette ,  James Aweya ,  Delfin Y. Montuno ,  Kent Felske

IPC: H04J3/14

CPC classification number: H04L41/12 ,  H04J3/0679

Abstract: Algorithms and data structure are described for constructing and maintaining a clock distribution tree (“CDT”) for timing loop avoidance. The CDT algorithms and data structure allows a node to make an automated and unattended path switch to the most desirable clock source in the network. In response to a network topology change, a clock root node distributes new clock paths to all nodes in the network. In particular, the root node calculates a new clock path for each affected node by building a clock source topology tree, and identifying from that tree a path to the network node from a clock source of higher or equal stratum relative to that network node. The root node then sends a network message to each node indicating the new path that the node should use. Each node receives the message and compares the new path with the existing path. If the paths are different then the node acquires the new path just received in the message. If the paths are the same then the node does nothing and discards the message.

Abstract translation: 描述了用于构建和维护用于定时回路的时钟分布树（“CDT”）的算法和数据结构。 CDT算法和数据结构允许节点将自动和无人值守的路径切换到网络中最理想的时钟源。 响应于网络拓扑变化，时钟根节点将新的时钟路径分配给网络中的所有节点。 特别地，根节点通过构建时钟源拓扑树来计算每个受影响节点的新时钟路径，并且从该树中识别来自相对于该网络节点的较高或相等层的时钟源到网络节点的路径。 根节点然后向每个节点发送一个网络消息，指示节点应该使用的新路径。 每个节点接收消息，并将新路径与现有路径进行比较。 如果路径不同，则节点获取刚刚在消息中接收到的新路径。 如果路径相同，则节点不执行任何操作并丢弃该消息。