公开(公告)号：US11996064B2

公开(公告)日：2024-05-28

申请号：US18187676

申请日：2023-03-22

Applicant: LAPIS Technology Co., Ltd.

Inventor： Koji Higuchi

IPC: G09G3/36

CPC classification number: G09G3/3696 ,  G09G3/3688 ,  G09G2310/027 ,  G09G2310/0291 ,  G09G2320/0233 ,  G09G2320/0276 ,  G09G2320/0673

Abstract: A display drive device includes a common voltage generating circuit that applies a voltage obtained by amplifying a reference common voltage to a common electrode as a common voltage, a reference gamma voltage generating circuit generating first to kth reference gamma voltages corresponding to predetermined gamma characteristics, a gamma compensation circuit receiving a voltage of the common electrode from the display panel and generating first to kth compensated reference gamma voltages obtained by adjusting voltage values of the first to kth reference gamma voltages based on a difference between the received voltage of the common electrode and the reference common voltage, and data drivers, each receives the first to kth compensated reference gamma voltages, generates grayscale voltages based on the first to kth compensated reference gamma voltages, selects a grayscale voltage corresponding to a brightness level indicated by a video signal, and supplies the grayscale voltage to each data line.

公开(公告)号：US11990102B2

公开(公告)日：2024-05-21

申请号：US18150787

申请日：2023-01-05

Applicant: LAPIS Technology Co., Ltd.

Inventor： Hiroshi Tsuchi

IPC: G09G3/36 ,  G09G3/20

CPC classification number: G09G3/3685 ,  G09G3/2096 ,  G09G3/3614 ,  G09G2310/08 ,  G09G2320/0209 ,  G09G2320/0247

Abstract: In a first output mode, a signal in which a data pulse having a positive polarity voltage value appears in a predetermined cycle is output as a positive polarity gradation data signal, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with a phase different from the positive polarity gradation data signal is output as a negative polarity gradation data signal. In a second output mode, the above positive polarity gradation data signal is generated, and a signal in which a data pulse having a negative polarity voltage value appears in the predetermined cycle with the same phase as the positive polarity gradation data signal is output as the negative polarity gradation data signal. The first and second output modes are alternatively executed, and the output mode is switched within a predetermined period at intervals of the predetermined period.

公开(公告)号：US11990069B2

公开(公告)日：2024-05-21

申请号：US18345965

申请日：2023-06-30

Applicant: LAPIS Technology Co., Ltd.

Inventor： Hiroyoshi Ichikura

IPC: G09G3/00 ,  G09G3/3275 ,  G09G3/36

CPC classification number: G09G3/006 ,  G09G3/3275 ,  G09G3/3688 ,  G09G2310/0291 ,  G09G2330/04 ,  G09G2330/12

Abstract: A display driver includes an amplifier circuit that outputs an output current based on a differential signal indicating a difference between a gradation voltage corresponding to a video signal and an output voltage to a source line of a display panel, thereby supplying the output voltage to the source line. An output current detection circuit generates a mirror current by copying the output current, and outputs an output current detection signal representing the mirror current. A failure determination circuit determines whether a failure is occurring or has occurred in the source line or not by comparing the level of the output current detection signal with a prescribed threshold value. The output current detection circuit includes a transistor that generates a mirror current by receiving the differential signal at a gate thereof, and a variable resistance that generates an output current detection signal upon receiving the generated mirror current.

公开(公告)号：US20240142545A1

公开(公告)日：2024-05-02

申请号：US18489848

申请日：2023-10-19

Applicant: LAPIS Technology Co., Ltd.

Inventor： Takahiro YONEDA

IPC: G01R31/40 ,  G01R23/00

CPC classification number: G01R31/40 ,  G01R23/005

Abstract: Provided is a power supply abnormality detection circuit capable of detecting a power supply abnormality using a logic circuit.
The power supply abnormality detection circuit includes a preset first dividing circuit part dividing a frequency of an input clock signal by a frequency of a first ratio and output the divided frequency, a second dividing circuit part dividing a frequency of the input clock signal by the frequency of the first ratio when a power supply voltage is a normal voltage, and dividing a frequency of an input signal by a frequency of a second ratio different from the first ratio and outputting the divided frequency when the power supply voltage is an abnormal voltage, and a comparison circuit part performing comparison of two signals of an output signal of the first dividing circuit part and an output signal of the second dividing circuit part.

公开(公告)号：US11955095B2

公开(公告)日：2024-04-09

申请号：US17696838

申请日：2022-03-16

Applicant: LAPIS Technology Co., Ltd.

Inventor： Hiroshi Tsuchi

IPC: G09G3/36 ,  G02F1/1362

CPC classification number: G09G3/36 ,  G02F1/136286 ,  G09G2300/0871 ,  G09G2330/02

Abstract: The disclosure provides an output circuit, a display driver including the output circuit and a display device. The disclosure includes a PMOS transistor switch that outputs a positive voltage signal from an output terminal when it is turned on, an NMOS transistor switch that outputs a negative voltage signal from the output terminal when it is turned on, and a voltage control circuit that supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the PMOS transistor switch is turned on to a high potential side to a back gate of the PMOS transistor switch and supplies a voltage obtained by shifting the level of a voltage of a source or a drain when the NMOS transistor switch is turned on to a low potential side to a back gate of the NMOS transistor switch.

公开(公告)号：US20240113035A1

公开(公告)日：2024-04-04

申请号：US18371546

申请日：2023-09-22

Applicant: LAPIS TECHNOLOGY CO., LTD. ,  LAPIS SEMICONDUCTOR CO., LTD.

Inventor： JUNICHI IKEDA ,  KAZUYUKI HONDA

IPC: H01L23/544 ,  H01L25/065

CPC classification number: H01L23/544 ,  H01L25/0657 ,  H01L24/16 ,  H01L2223/54426 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2225/06596

Abstract: A semiconductor device includes: a first semiconductor chip on which a first alignment mark, a second alignment mark, first and second terminals for measuring conduction, a wiring that electrically connects the first alignment mark and the first terminal, and a wiring that electrically connects the second alignment mark and the second terminal are provided; and a second semiconductor chip on which a third alignment mark, a fourth alignment mark, and a wiring that electrically connects the third alignment mark and the fourth alignment mark are provided and which is bonded to the first semiconductor chip in such a way that the first alignment mark and the third alignment mark overlap each other, and the second alignment mark and the fourth alignment mark overlap each other.

公开(公告)号：US20240112647A1

公开(公告)日：2024-04-04

申请号：US18371550

申请日：2023-09-22

Applicant: LAPIS TECHNOLOGY CO., LTD.

Inventor： HIROAKI ISHII

IPC: G09G3/36

CPC classification number: G09G3/3688 ,  G09G3/3677 ,  G09G2310/0278 ,  G09G2310/0291

Abstract: A source driver includes an output buffer. The output buffer includes: an amplifying unit; a first current control unit that includes a first constant current source and a second constant current source; and a second current control unit that includes a third constant current source and a fourth constant current source. The first constant current source is disposed on a first supply line. The second constant current source is disposed on a second supply line. The third constant current source is connected in parallel to the first supply line, supplies the first power supply voltage to the amplifying unit, and allows turning on and off the supply. The fourth constant current source is connected in parallel to the second supply line, supplies the second power supply voltage to the amplifying unit, and allows turning on and off the supply.

公开(公告)号：US20240112607A1

公开(公告)日：2024-04-04

申请号：US18470010

申请日：2023-09-19

Applicant: LAPIS Technology Co., Ltd.

Inventor： Takahiro IMAYOSHI

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/0275 ,  G09G2310/0291 ,  G09G2310/08

Abstract: A display device includes drivers and a selector that supplies gradation voltage signals to data lines selectively. The source drivers include a first source driver having a first output buffer outputting a switch signal and a second driver having a second output buffer. The first output buffer has first and second transistors connected via an output terminal outputting the switch signal and turned on and off in a complementary manner. The second output buffer has third and fourth transistors connected via an output terminal outputting the switch signal and turned on and off in a complementary manner. The output terminals of the first and second output buffers are electrically connected. The first source driver has a buffer control circuit that controls a voltage to be applied to each transistor in order to create a high-impedance period where the first and second transistors are turned off at the same time.

公开(公告)号：US20240106327A1

公开(公告)日：2024-03-28

申请号：US18468738

申请日：2023-09-18

Applicant: LAPIS Technology Co., Ltd.

Inventor： Ryuu SOGA ,  Tomoyuki MAEDA

IPC: H02M3/156 ,  H02M1/00

CPC classification number: H02M3/156 ,  H02M1/0012

Abstract: A semiconductor device includes: a storage circuit configured to be connected to a regulator circuit having characteristics to be identified using one or more values and store values identifying characteristics of the regulator circuit; and an electronic fuse controller including an input configured to be connected to an electronic fuse circuit including one or more electronic fuses, an output configured to be connected to the storage circuit, a reading control circuit, and a characteristic control circuit, in which the reading control circuit includes a reading circuit configured to read values from at least part of the electronic fuses through the input in a reading period, and the characteristic control circuit is configured to generate identification data configured to identify the characteristics based on a signal from the reading circuit and supply the identification data to the storage circuit through the output in an identifying period different from the reading period.

公开(公告)号：US20240105090A1

公开(公告)日：2024-03-28

申请号：US18470373

申请日：2023-09-19

Applicant: LAPIS Technology Co., Ltd.

Inventor： Hiroshi TSUCHI

IPC: G09G3/20

CPC classification number: G09G3/20 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2330/028

Abstract: A digital-to-analog conversion circuit includes a differential amplifier outputting 2N voltage levels dividing first and second voltages and a decoder distributing and supplying one of first and second voltages to a plurality of input terminals of the differential amplifier on the basis of digital data of N bits, and the differential amplifier includes 2K differential pairs including an inverting input terminal to which an output voltage is commonly input and a non-inverting input terminal to which one of voltages received by the plurality of input terminals is input and having output pairs commonly connected with each other and a tail current control circuit individually controlling current ratios of tail currents supplied to the differential pairs on the basis of a predetermined bit of digital data, in which N is equal to or greater than 3, and K is a positive number less than N.